Display substrate and display device

ABSTRACT

A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate, a sub-pixel includes an organic light emitting element and a pixel circuit, the organic light emitting element includes a first electrode, a light emitting layer and a second electrode which are stacked, the second electrode is electrically connected to the pixel circuit. The display substrate further includes an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer, and a third conductive layer, the source-drain metal layer includes a first power signal line, and the third conductive layer includes a second power signal line; the display substrate further includes reset power signal lines, the reset power signal lines include a first reset power signal line and a second reset power signal line which are electrically connected to the pixel circuit.

This application is a continuation application of U.S. Ser. No. 16/977,188 filed on Sep. 1, 2020 which is a U.S. National Phase Entry of International Application No. PCT/CN2019/122129 filed on Nov. 29, 2019, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

At least one embodiment of the present disclosure relates to a display substrate and a display device.

BACKGROUND

Organic light emitting diodes have advantages of self-luminescence, high efficiency, bright color, thin and light, power saving, curling, wide using temperature range, and so on, and have been gradually applied to fields such as large-area display, lighting, vehicle display, and the like.

SUMMARY

At least one embodiment of the present disclosure provides a display substrate and a display device.

At least an embodiment of the present disclosure provides an array substrate, including: a base substrate and a plurality of sub-pixels arranged on the base substrate, an active semiconductor layer on the base substrate, a first conductive layer located on a side of the active semiconductor layer away from the base substrate, a second conductive layer located on a side of the first conductive layer away from the base substrate, a source-drain metal layer located on a side of the second conductive layer away from the base substrate, and a third conductive layer located on a side of the source-drain metal layer away from the base substrate. At least part of the plurality of sub-pixels include an organic light emitting element and a pixel circuit for driving the organic light emitting element to emit light, the organic light emitting element includes a first electrode, a light emitting layer and a second electrode which are stacked, the second electrode of the organic light emitting element is located between the light emitting layer and the base substrate, the second electrode of the organic light emitting element is electrically connected to the pixel circuit, the pixel circuit includes a plurality of transistors, the plurality of sub-pixels are arranged along a first direction or a second direction, and the first direction is intersected with the second direction. The active semiconductor layer includes channels, source regions and drain regions of the plurality of transistors. The source-drain metal layer includes a first power signal line, and the third conductive layer includes a second power signal line; the display substrate further includes reset power signal lines, the reset power signal lines include a first reset power signal line and a second reset power signal line; the first reset power signal line and the second reset power signal line are electrically connected to the pixel circuit and configured to provide a reset signal; and the first power signal line and the second power signal line are electrically connected to the pixel circuit.

For example, the display substrate further includes data lines, a data line is electrically connected to the pixel circuit to provide a data signal; at least one pixel circuit includes a driving transistor, a first light emitting control transistor, a second light emitting control transistor and a first connection portion, the first connection portion is located in the source-drain metal layer, a first electrode of the first light emitting control transistor is electrically connected to the first power signal line through a first via hole, a second electrode of the first light emitting control transistor is electrically connected to a first electrode of the driving transistor, a first electrode of the second light emitting control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the second light emitting control transistor is electrically connected to the first connection portion through a second via; a first straight line extending along the first direction passes through at least one first via hole and at least one second via.

For example, the pixel circuit further includes a second connection portion, the second connection portion is arranged in the same layer as the second power signal line, the second connection portion is electrically connected to the first connection portion through a third via hole, and the second power signal line is electrically connected to the first power signal line through a fourth via; a second straight line extending along the first direction passes through at least one fourth via hole and at least one third via.

For example, the plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels and a plurality of third color sub-pixels, and in a direction perpendicular to the base substrate, the second electrode of the organic light emitting element of at least one of the plurality of third color sub-pixels overlaps with at least two data lines.

For example, the second electrode of the organic light emitting element of the at least part of the plurality of sub-pixels includes a main electrode and a connection electrode, the connection electrode is electrically connected to the second light emitting control transistor, the connection electrode of at least one of the plurality of second color sub-pixels and the connection electrode of at least one of the plurality of first color sub-pixels extend along the second direction, and the connection electrode of at least one of the plurality of third color sub-pixels extends along the first direction.

For example, the first reset power signal line extends along the first direction, and the second reset power signal line extends along the second direction.

For example, the first reset power signal line is disposed in the second conductive layer, and the second reset power signal line is disposed in the source-drain metal layer.

For example, the connection electrode of the at least part of the plurality of sub-pixels is electrically connected to the second connection portion through a fifth via hole, the first conductive layer further includes a light emitting control signal line extending along the first direction, the light emitting control signal line is electrically connected to gate electrodes of the first light emitting control transistor and the second light emitting control transistor, an orthographic projection of at least part of the second via hole of at least one sub-pixel on the base substrate is located at one side of an orthographic projection of the light emitting control signal line on the base substrate, and an orthographic projection of at least part of the fifth via hole on the base substrate is located at the other side of the orthographic projection of the light emitting control signal line on the base substrate.

For example, in at least one second color sub-pixel, the fifth via hole is closer to a center of the main electrode than the third via hole is; and in at least one first color sub-pixel, the fifth via hole is closer to a center of the main electrode than the third via hole is.

For example, an orthographic projection of the second electrode of the organic light emitting element of the first color sub-pixel on a straight line extending along the first direction overlaps with orthographic projections of three first connection portions respectively located in three sub-pixels, and the three sub-pixels include one first color sub-pixel, one second color sub-pixel and one third color sub-pixel.

For example, an orthographic projection of the second electrode of the organic light emitting element of the first color sub-pixel on a straight line extending along the first direction overlaps with orthographic projections of three second connection portions respectively located in three sub-pixels, and the three sub-pixels include one first color sub-pixel, one second color sub-pixel and one third color sub-pixel.

For example, in at least one of the plurality of third color sub-pixels, the second electrode of the organic light emitting element does not overlap with a channel of the driving transistor which controls the organic light emitting element of the third color sub-pixel in the direction perpendicular to the base substrate.

For example, in at least one of the plurality of first color sub-pixels, the second electrode of the organic light emitting element overlaps with a channel of the driving transistor which controls the organic light emitting element of the first color sub-pixel in the direction perpendicular to the base substrate.

For example, in at least one sub-pixel, the second electrode of the organic light emitting element exposes the third via.

For example, in each of the plurality of first color sub-pixels, an orthographic projection of the second electrode of the organic light emitting element on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate; in each of the plurality of second color sub-pixels, an orthographic projection of the second electrode of the organic light emitting element on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate; and in each of the plurality of third color sub-pixels, an orthographic projection of the second electrode of the organic light emitting element on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate.

For example, among at least one of the plurality of first color sub-pixels, at least one of the plurality of second color sub-pixels and at least one of the plurality of third color sub-pixels, the pixel circuit further includes a storage capacitor, a first electrode of the storage capacitor is located in the second conductive layer, a second electrode of the storage capacitor is located in the first conductive layer, and the first electrode of the storage capacitor and the second electrode of the storage capacitor overlap in the direction perpendicular to the base substrate and have an overlapping area; the overlapping area in the at least one of the plurality of first color sub-pixels is different from the overlapping area in the at least one of the plurality of second color sub-pixels; and/or the overlapping area in the at least one of the plurality of first color sub-pixels is different from the overlapping area in the at least one of the plurality of third color sub-pixels.

For example, the overlapping area in the first color sub-pixel is the greatest among the at least one of the plurality of first color sub-pixels, the at least one of the plurality of second color sub-pixels and the at least one of the plurality of third color sub-pixels.

For example, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

For example, at least one first reset power signal line is electrically connected to at least one second reset power signal line.

For example, the first reset power signal line is electrically connected to the second reset power signal line through a sixth via.

For example, the second conductive layer further includes a signal pattern, the signal pattern is located between the first reset power signal line and the first electrode of the storage capacitor in the second direction, and the signal pattern is configured to access the reset signal.

For example, the first conductive layer further includes a scanning signal line extending along the first direction, the pixel circuit of the at least part of the plurality of sub-pixels further includes a data writing transistor, a first electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, a second electrode of the data writing transistor is configured to be electrically connected to the data line to receive a data signal, and a gate electrode of the data writing transistor is configured to be electrically connected to the scanning signal line to receive a scan signal; the first reset power signal line extends along the first direction, and in the second direction, an orthographic projection of the signal pattern on the base substrate is located between an orthographic projection of the scanning signal line on the base substrate and an orthographic projection of the first reset power signal line on the base substrate.

At least an embodiment of the present disclosure provides a display device, including the display substrate as mentioned above.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described in the following. It is obvious that the described drawings in the following are only related to some embodiments of the present disclosure and thus are not limitative of the present disclosure.

FIG. 1A is a planar diagram of an array substrate provided by an embodiment of the present disclosure;

FIG. 1B is a partial cross-sectional diagram of the array substrate shown in FIG. 1A;

FIG. 1C is a planar diagram of an array substrate provided by an embodiment of the present disclosure;

FIG. 1D and FIG. 1E are planar diagrams of driving transistors of a first color sub-pixel and a second color sub-pixel, respectively;

FIG. 2 is a schematic flow diagram of a manufacturing method for an array substrate provided by an embodiment of the present disclosure;

FIG. 3 is a simulation curve of a data signal input to sub-pixel of each color and a saturation current flowing through an organic light emitting element of sub-pixel of each color in a second example of an embodiment of the present disclosure;

FIG. 4 is a curve of gate voltages and saturation currents of driving transistors with different channel width-length ratios provided by an embodiment of the present disclosure;

FIG. 5A-FIG. 5C are relationship diagrams of a channel width-length ratio of a driving transistor and a charging rate in sub-pixel of each color;

FIG. 6 is a schematic block diagram of a display substrate provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of repeating units of a display substrate provided by an embodiment of the present disclosure;

FIG. 8 is a planar diagram of a display substrate provided by an embodiment of the present disclosure;

FIG. 9A-FIG. 10A are schematic diagrams of layers of a pixel circuit provided by some embodiments of the present disclosure;

FIG. 10B and FIG. 10C are cross-sectional diagrams taken along a line AA′ and a line BB′ shown in FIG. 10A;

FIG. 11A is a partial structural diagram of an array substrate provided by an example of an embodiment of the present disclosure;

FIG. 11B is a schematic diagram of an arrangement structure of pixels shown in FIG. 11A; and

FIG. 12 is a partial structural diagram of an array substrate provided by another example of an embodiment.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects.

In a research, the inventor of the present application found that in a case where the organic light emitting diode is used in the field of vehicle display, the vehicle screen needs to have high brightness, for example, the brightness reaches 800 nits or even more than 1000 nits. Therefore, it is particularly important to realize the design of high-brightness vehicle screens. In a current vehicle display device, the red light, green light, and blue light have different brightness ratios in white light, and the organic light emitting elements of different color sub-pixels use different materials, resulting in different current efficiency of different color sub-pixels, and therefore when channel width-length ratios of driving transistors in sub-pixels of respective colors are designed to have the same value, there will be insufficient blue light in a case of designing a high-brightness vehicle screen, thus restricting the maximum brightness that the vehicle screen can achieve.

Embodiments of the present disclosure relate to an array substrate and a manufacturing method therefor, an organic light emitting diode display device and a display substrate. The array substrate includes: a base substrate and a plurality of repeating units arranged in an array along a first direction and a second direction on the base substrate, the first direction intersects the second direction. Each of the repeating units includes a first color sub-pixel and a second color sub-pixel, each sub-pixel includes an organic light emitting element and a pixel circuit for driving the organic light emitting element, and the pixel circuit includes a driving circuit, the driving circuit of the first color sub-pixel includes a first driving transistor, and the driving circuit of the second color sub-pixel includes a second driving transistor, and a channel width-length ratio of the first driving transistor is greater than a channel width-length ratio of the second driving transistor. The embodiments of the present disclosure can improve the brightness of a display device including the array substrate by optimizing channel width-length ratios of driving transistors of sub-pixels with different colors on the array substrate.

The array substrate and the manufacturing method therefor, the organic light emitting diode display device, and the display substrate provided by the embodiments of the present disclosure will be described below with reference to the drawings.

FIG. 1A is a planar diagram of an array substrate provided by an embodiment of the present disclosure; and FIG. 1B is a partial cross-sectional diagram of the array substrate shown in FIG. 1A along a line AA. As shown in FIG. 1A, an embodiment of the present disclosure provides an array substrate, which includes a base substrate 100 and a first color sub-pixel 110 and a second color sub-pixel 120 on the base substrate 100. The first color sub-pixel 110 includes a first driving transistor 111, the second color sub-pixel 120 includes a second driving transistor 121, and a channel width-length ratio W1/L1 of the first driving transistor 111 is greater than a channel width-length ratio W2/L2 of the second driving transistor 121. That is, a channel width of the first driving transistor 111 is W1 and a channel length of the first driving transistor 111 is L1, a channel width of the second driving transistor 121 is W2 and a channel length of the second driving transistor 121 is L2, and W1, L1, W2 and L2 satisfies a relationship of W1/L1>W2/L2. FIG. 1A schematically shows that the first driving transistor and the second driving transistor have the same channel length, but have different channel widths. The embodiments of the present disclosure are not limited thereto, and the channel widths of the first driving transistor and the second driving transistor may be the same, but the channel lengths are different, or the channel widths and channel lengths of the first driving transistor and the second driving transistor are all different.

The embodiments of the present disclosure can improve the brightness of the display device including the array substrate by optimizing the channel width-length ratios of the driving transistors of the sub-pixels with different colors on the array substrate.

In some examples, current efficiency of the first color sub-pixel is less than current efficiency of the second color sub-pixel. The current efficiency here refers to the light emitting intensity of sub-pixel of each color at a unit current (unit: candela per ampere, cd/A). Because the current efficiency of sub-pixels with different colors are different, by setting the channel width-length ratios of the driving transistors of sub-pixels with different colors to be different, in a case where white light displayed by the display device including the array substrate is at the highest gray scale, a phenomenon of insufficient brightness of the first color is avoided.

In some examples, the first color sub-pixel 110 is a blue sub-pixel, and the second color sub-pixel 120 is a red sub-pixel or a green sub-pixel. In the embodiments of the present disclosure, by setting the channel width-length ratio of the driving transistor of the blue sub-pixel to be greater than the channel width-length ratio of the driving transistor of the red sub-pixel or the green sub-pixel, in a case where white light displayed by the display device including the array substrate is at the highest gray scale, a phenomenon of insufficient brightness of blue light is avoided, so that the white balance color coordinate of the white light at the highest gray level can be avoided from deviating from the design value.

The above-mentioned white balance refers to the balance of the white light, that is, an indicator of the accuracy of the white light formed by mixing the three primary colors of red, green, and blue displayed by the display device.

For example, the first color sub-pixel 110 may also be a blue sub-pixel, and the second color sub-pixel 120 may also be a yellow sub-pixel.

FIG. 1C is a planar diagram of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 1C, the array substrate may further include a third color sub-pixel 130, and the third color sub-pixel 130 includes a third driving transistor 131.

For example, the first color sub-pixel 110 is a blue sub-pixel, the second color sub-pixel 120 is a red sub-pixel, and the third color sub-pixel 130 is a green sub-pixel.

For example, the channel width-length ratio of the second driving transistor 121 of the red sub-pixel may be the same as the channel width-length ratio of the third driving transistor 131 of the green sub-pixel, so as to facilitate manufacturing. However, the embodiments are not limited to this case, and the channel width-length ratios of the driving transistors of the red sub-pixel and the green sub-pixel may be adjusted according to the brightness requirements of each color light in a case where the display device realizes high-brightness display.

In some examples, a ratio of the channel width-length ratio of the driving transistor of the red sub-pixel, the channel width-length ratio of the driving transistor of the green sub-pixel, and the channel width-length ratio of the driving transistor of the blue sub-pixel is about 1:(0.7-1.3):(1.5-2.5), so that in a case where the brightness of white light displayed by the display device is 800 nits or even 1000 nits, the phenomenon of insufficient brightness of blue light will not occur.

In some examples, the ratio of the channel width-length ratio of the driving transistor of the red sub-pixel, the channel width-length ratio of the driving transistor of the green sub-pixel, and the channel width-length ratio of the driving transistor of the blue sub-pixel may be 1:1:2, so as to facilitate actual manufacturing process.

In some examples, FIG. 1D and FIG. 1E are planar diagrams of driving transistors of a first color sub-pixel and a second color sub-pixel, respectively. As shown in FIG. 1D and FIG. 1E, a portion of an active layer of the first driving transistor 111 of the first color sub-pixel 110 that overlaps with a gate electrode 114 is the channel of the first driving transistor 111, and the channel width-length ratio W1/L1 of the first driving transistor 111 may be 5/25. A portion of an active layer of the second driving transistor 121 of the second color sub-pixel 120 that overlaps with a gate electrode 124 is the channel of the second driving transistor 121, and the channel width-length ratio W2/L2 of the second driving transistor 121 may be 3/30. For example, as shown in FIG. 1D, center points of portions of the active layer of the first driving transistor 111 overlapping with edges of the gate electrode 114 extending in the X direction are O and O′, respectively, and a center line C1 of the portion of the active layer of the first driving transistor 111 overlapping with the gate electrode 114 extends from O to O′. The “length” in the above channel width-length ratio refers to the length L1 of the center line C1, and the “width” in the channel width-length ratio refers to a size of the portions of the active layer of the first driving transistor 111 overlapping with edges of the gate electrode 114 extending in the X direction. Similarly, as shown in FIG. 1E, the “length” in the channel width-length ratio of the second driving transistor 121 refers to the length L2 of the center line C2, and the “width” in the channel width-length ratio refers to a size of portions of the active layer of the second driving transistor 121 overlapping with edges of the gate electrode 124 extending in the X direction.

For example, as shown in FIG. 1D and FIG. 1E, the channel width-length ratio of the driving transistor of the blue sub-pixel may be 5/25, and the channel width-length ratio of the green sub-pixel and the channel width-length ratio of the red sub-pixel may be 3/30.

The embodiments of the present disclosure do not limit the specific channel width-length ratio of the driving transistor of sub-pixel of each color, as long as the ratio of the channel width-length ratios of the driving transistors of sub-pixels of respective colors satisfies the above ratio range.

In some examples, sub-pixel of each color in the array substrate includes an organic light emitting element, the organic light emitting element includes a light emitting layer, and a first electrode and a second electrode on two sides of the organic light emitting layer, one of the first electrode and the second electrode is connected to the driving transistor, that is, the array substrate in the embodiments of the present disclosure is an array substrate applied in an organic light emitting diode display device.

For example, as shown in FIG. 1A and FIG. 1B, the first color sub-pixel 110 includes a first organic light emitting layer 112, a first electrode 114 on a side of the first organic light emitting layer 112 away from the base substrate 100, and a second electrode 113 on a side of the first organic light emitting layer 112 facing the base substrate 100, and the second electrode 113 is connected to one of a source electrode and a drain electrode of the first driving transistor 111. The second color sub-pixel 120 includes a second organic light emitting layer 122, a first electrode 124 on a side of the second organic light emitting layer 122 away from the base substrate 100, and a second electrode 123 on a side of the second organic light emitting layer 122 facing the base substrate 100, and the second electrode 123 is connected to one of a source electrode and a drain electrode of the second driving transistor 121. The first electrodes of the sub-pixels with different colors shown in FIG. 1B may be a common electrode, and the first electrodes of the sub-pixels with different colors may be formed of the same layer and the same material to reduce the process.

For example, as shown in FIG. 1C, the second electrode 133 of the organic light emitting element in the third color sub-pixel 130 is connected to one of a source electrode and a drain electrode of the third driving transistor 131.

For example, as shown in FIG. 1B, the array substrate further includes a pixel defining layer 101 between adjacent organic light emitting layers and a planarization layer 102 between the second electrode and the driving transistor.

For example, the first electrode of sub-pixel of each color may be a cathode, and the cathode is also used as a connection electrode for transmitting a negative voltage of sub-pixel of each color, and has better conductivity and a lower work function value. The embodiment includes but is not limited thereto. The second electrode of sub-pixel of each color may be an anode. The anode is also used as a connection electrode for transmitting a positive voltage of sub-pixel of each color, and has better conductivity and a higher work function value. The embodiment includes but is not limited thereto.

For example, the driving transistor of sub-pixel of each color in the embodiments of the present disclosure may be a low-temperature polysilicon (LTPS) thin film transistor. For a sub-pixel including the low-temperature polysilicon thin film transistor, the saturation current I flowing through the organic light emitting element satisfies the following relationship:

I=K1*(W/L)*(Vgs−Vth)²,  (1)

In the above relationship (1), W and L are the channel width and the channel length of the driving transistor, respectively, K1 is related to the channel mobility of the driving transistor and the channel capacitance per unit area, and Vgs and Vth are a voltage between the gate electrode and the source electrode and a threshold voltage of the driving transistor, respectively, and K1 is a coefficient determined by characteristics of the channel of each driving transistor, such as the channel mobility.

The above saturation current I, and the brightness Y and the current efficiency E of the sub-pixel satisfy the following relationship:

I=(Y*S)/E,  (2)

From the above relationship (1) and relationship (2), the following relationship is obtained:

I=(Y*S)/E=K1*(W/L)*(Vgs−Vth)²,  (3)

According to the relationship (3), it can be obtained that the channel width-length ratio of the driving transistor of sub-pixel of each color satisfies the following relationship:

W/L=K2*(Y/E),  (4)

K2 is a coefficient related to K1, (Vgs−Vth)² and S. Therefore, the channel width-length ratio of the first driving transistor of the first color sub-pixel, the channel width-length ratio of the second driving transistor of the second color sub-pixel, and the channel width-length ratio of the third driving transistor of the third color sub-pixel all satisfy the above relationship (4).

In the above relationships (2-4), S is the area of the effective display region included in the array substrate. In the display device including the array substrate provided by the embodiments of the present disclosure, S is the area of the effective display region of the display screen of the display device. In the embodiments of the present disclosure, the above Y is the brightness of sub-pixel of each color in a case where white light formed by mixing light of sub-pixels of respective colors is in white balance.

For example, in the embodiments of the present disclosure, the case that Y is the maximum brightness for display of sub-pixel of each color after passing through the display screen where white light formed by mixing light of sub-pixels of respective colors is at the highest gray level is described as an example. For example, Y may be the display brightness of the light emitted by the organic light emitting element after passing through the display screen. For example, because the display side of the display device including the above array substrate usually has a circular polarizer, a touch screen, etc., the overall transmittance T of the display screen for white light is generally about 0.4, and the overall transmittances of light with different colors are slightly different. For facilitating calculation, in this embodiment, the overall transmittance of the screen for white light, red light, green light, and blue light are all 0.42, and the embodiment includes but is not limited to this case.

For example, according to the above relationship (4), the channel width-length ratios of the driving transistors in the red sub-pixel, the green sub-pixel, and the blue sub-pixel included in the array substrate satisfies the following ratio relationship (5):

(W/L)_(R):(W/L)_(G):(W/L)_(B)=[K2_(R)*(Y _([R]) /E _(R))]:[K ₂ G*(Y _([G]) /E _(G))]:[K ₂ B*(Y _([B]) /E _(B))].

For example, assuming that the uniformity difference caused in the process is not considered, the channel mobility and the channel capacitance per unit area of the driving transistor in sub-pixel of each color have the same value.

Assuming that Vth compensation is considered, for example, for the driving transistor, the voltage difference between the gate electrode and the source electrode Vgs=Vdata+Vth−Vdd, the driving transistor is in a saturated state, and charges the organic light emitting element, the output saturation current I satisfies:

$\begin{matrix} \begin{matrix} {I = {K1^{*}\left( {W/L} \right)^{*}\left( {{Vgs} - {Vth}} \right)^{2}}} \\ {= {K1^{*}\left( {W/L} \right)^{*}\left( {{Vdata} + {Vth} - {Vdd} - {Vth}} \right)^{2}}} \\ {= {K1^{*}\left( {W/L} \right)^{*}\left( {{Vdata} - {Vdd}} \right)^{2}}} \end{matrix} & (6) \end{matrix}$

The above Vdata is a data signal input to a sub-pixel including a driving transistor, and Vdd is a power supply voltage input to the driving transistor. For each sub-pixel, in a case where the power supply voltage Vdd is unchanged, the magnitude of the driving current I is directly related to the data signal Vdata (that is, the display data voltage). In a case where the data signal Vdata is equal to the power supply voltage Vdd, the output current I of the driving transistor is zero, that is, no current flows through the organic light emitting element. In this case, the sub-pixel including the organic light emitting element does not emit light, that is, displays black. In a case where the data signal Vdata is not equal to the power supply voltage Vdd, the output current I of the driving transistor is not zero, that is, there is a current flowing through the organic light emitting element. In this case, the sub-pixel including the organic light emitting element emits light, and the greater the difference between the data signal Vdata and the power supply voltage Vdd is, the greater the output current I is, the higher the gray scale displayed by the corresponding sub-pixel is, and the greater the brightness of the sub-pixel is.

Considering the uniformity difference caused by the actual process, after calculating the ratio of the channel width-length ratios of the driving transistors of sub-pixels of respective colors through the relationship (5) and the relationship (6), the ratio may be adjusted in a range to meet the process. For example, in a case where the ratio of the channel width-length ratios of the driving transistors of sub-pixels of respective colors is calculated by the above ratio relationship to be 1:0.97:2.03, it can be considered to adjust the above ratio to 1:1:2 for the convenience of design and manufacturing process.

FIG. 2 is a schematic flow diagram of a manufacturing method for an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 2, the method for manufacturing the driving transistor of sub-pixel of each color provided by embodiments of the present disclosure includes the following steps.

S101: acquiring an optical parameter of a display device including the array substrate, and calculating preset brightness of sub-pixel of each color according to the optical parameter.

In some examples, the array substrate may include sub-pixels of three colors, namely a blue sub-pixel (the first color sub-pixel), a red sub-pixel (the second color sub-pixel), and a green sub-pixel (the third color sub-pixel). The object color tristimulus values of blue light emitted by the blue sub-pixel is (X_([B]), Y_([B]), Z_([B])), and the object color tristimulus values of green light emitted by the green sub-pixel is (X_([G]), Y_([G]), Z_([G])), the object color tristimulus values of red light emitted by the red sub-pixel (X_([R]), Y_([R]), Z_([R])), and the object color tristimulus values of white light formed by mixing the blue light, the green light and the red light is (X_([W]), Y_([W]), Z_([W])). The object color tristimulus values refer to the number of red, green, and blue primary colors needed to match the reflected light of the object (the three primary colors here are not physical real colors, but fictional imaginary colors), and also refer to the colorimetric values of the object color. Object color refers to the color of the object seen by eyes, that is, the color of light reflected or transmitted by the object.

For example, the object color tristimulus values X, Y and Z of sub-pixel of each color above satisfy the following relationship:

X=∫ ₃₈₀ ⁷⁸⁰⁻ x(λ)Φ(λ)dλ, Y _(M)=∫₃₈₀ ⁷⁸⁰⁻ y(λ)Φ(λ)dλ, Z=∫ ₃₈₀ ⁷⁸⁰⁻ z(λ)Φ(λ)dλ  (7)

In the above relationship (7), Φ(λ) represents a function of the emission spectrum of light with a wavelength of 2 and the wavelength. The above x(λ), y(λ), and z(λ) represent the spectral tristimulus values, which are also known as the CIE1931 standard colorimetric observer spectral tristimulus values. It should be noted that Y in the tristimulus values of each color light may represent the maximum brightness that can be achieved by the brightness of the color light to be matched in a case where the white light formed by mixing in the display device is in the white balance state. Therefore, Y_([B]), Y_([G]), Y_([R]), and Y_([W]) can be the maximum brightness of blue light, green light, red light, and white light in a case where the white light is in the white balance state, and the maximum brightness are also the preset brightness of each color light in the embodiments of the present disclosure.

For example, the color coordinate center values of each color light is (x, y, z), and the color coordinate center values of each color light and the object color tristimulus values satisfy the following relationship:

x=X/(X+Y+Z),

y=Y/(X+Y+Z),

z=Z/(X+Y+Z),  (8)

It can be obtained from the above relationship (8) that x+y+z=1.  (9)

According to the relationship of the above color coordinates and the colorimetric value of the object color, after obtaining the preset color coordinate of sub-pixel of each color, the ratio relationship of the three parameters in the colorimetric value of the object color can be obtained.

For example, according to the additive color mixing theory, the colorimetric value of the object color of white light formed by mixing red light, green light, and blue light, and the colorimetric values of the object color of the red light, green light, and blue light satisfy the following relationship:

X _([W]) =X _([B]) +X _([G]) +X _([R]),

Y _([W]) =Y _([B]) +Y _([G]) +Y _([R]),

Z _([W]) =Z _([B]) +Z _([G]) +Z  (10)

The above relationship is written in matrix form as:

$\begin{matrix} {{\begin{bmatrix} X_{\lbrack W\rbrack} \\ Y_{\lbrack W\rbrack} \\ Z_{\lbrack W\rbrack} \end{bmatrix} = {\begin{bmatrix} \frac{X_{\lbrack R\rbrack}}{Y_{\lbrack R\rbrack}} & \frac{X_{\lbrack G\rbrack}}{Y_{\lbrack G\rbrack}} & \frac{X_{\lbrack B\rbrack}}{Y_{\lbrack B\rbrack}} \\ 1 & 1 & 1 \\ \frac{Z_{\lbrack R\rbrack}}{Y_{\lbrack R\rbrack}} & \frac{Z_{\lbrack G\rbrack}}{Y_{\lbrack G\rbrack}} & \frac{Z_{\lbrack B\rbrack}}{Y_{\lbrack B\rbrack}} \end{bmatrix}*\begin{bmatrix} Y_{\lbrack R\rbrack} \\ Y_{\lbrack G\rbrack} \\ Y_{\lbrack B\rbrack} \end{bmatrix}}},} & (11) \end{matrix}$

The maximum brightness Y_([R]), Y_([G]), and Y_([B]) of the above red light, green light, and blue light can be obtained by the inverse matrix:

$\begin{matrix} {{\begin{bmatrix} Y_{\lbrack R\rbrack} \\ Y_{\lbrack G\rbrack} \\ Y_{\lbrack B\rbrack} \end{bmatrix} = {\begin{bmatrix} \frac{X_{\lbrack R\rbrack}}{Y_{\lbrack R\rbrack}} & \frac{X_{\lbrack G\rbrack}}{Y_{\lbrack G\rbrack}} & \frac{X_{\lbrack B\rbrack}}{Y_{\lbrack B\rbrack}} \\ 1 & 1 & 1 \\ \frac{Z_{\lbrack R\rbrack}}{Y_{\lbrack R\rbrack}} & \frac{Z_{\lbrack G\rbrack}}{Y_{\lbrack G\rbrack}} & \frac{Z_{\lbrack B\rbrack}}{Y_{\lbrack B\rbrack}} \end{bmatrix}^{- 1}*\begin{bmatrix} X_{\lbrack W\rbrack} \\ Y_{\lbrack W\rbrack} \\ Z_{\lbrack W\rbrack} \end{bmatrix}}},} & (12) \end{matrix}$

Therefore, proportions of red light, green light, and blue light in white light are: Y_([R])/Y_([W]), Y_([G])/Y_([W]), Y_([B])/Y_([W]), respectively.

In some examples, when designing the ratio of the channel width-length ratios of the driving transistors of sub-pixels with different colors, the optical parameter after the array substrate is applied to an organic light emitting diode display device needs to be considered.

In some examples, the optical parameter may include a target brightness (the preset brightness, for example, the maximum brightness after passing through the display screen) of the white light emitted by the organic light emitting diode display device, a target white balance coordinate (the preset white balance coordinate) of the white light, and a target color coordinate center value (the preset color coordinate) of sub-pixel of each color, such as the preset color coordinates of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel.

For example, a step of calculating the preset brightness of sub-pixel of each color according to the optical parameter includes: obtaining the colorimetric value (X_([W]), Y_([W]), Z_([W])) of the object color of white light according to the preset white balance coordinate of white light and the preset brightness of white light; and calculating the preset brightness of sub-pixel of each color according to the matrix relationship (12) and the preset color coordinate of sub-pixel of each color.

For example, in the first example of the embodiments of the present disclosure, the preset brightness of white light may be set to 800 nits, and the preset white balance coordinate of white light may be (0.30, 0.32). Because Y in the colorimetric value of the object color of white light is 800, the colorimetric value of the object color of white light is (750, 800, 950) according to the relationships (8-9).

For example, the central value of the preset color coordinate of the red sub-pixel may be (0.685, 0.315), the central value of the preset color coordinate of the green sub-pixel may be (0.252, 0.718), the central value of the preset color coordinate of the blue sub-pixel may be (0.135, 0.05). The embodiments of the present disclosure are not limited thereto, and the values can be selected according to specific requirements.

According to the above relationships (8-10) and the relationship (12), the following relationship is obtained:

$\begin{bmatrix} Y_{M{\lbrack R\rbrack}} \\ Y_{M{\lbrack G\rbrack}} \\ Y_{M{\lbrack B\rbrack}} \end{bmatrix} = {\begin{bmatrix} \frac{0.685}{0.315} & \frac{0.252}{0.718} & \frac{0.135}{0.05} \\ 1 & 1 & 1 \\ \frac{1 - {0.685} - {{0.3}15}}{0.315} & \frac{1 - 0.252 - {{0.7}18}}{0.718} & \frac{1 - 0.135 - {{0.0}5}}{0.05} \end{bmatrix}^{- 1}*{\quad{\begin{bmatrix} {750} \\ {800} \\ {950} \end{bmatrix} = \begin{bmatrix} 184.1 \\ 559.1 \\ {56.8} \end{bmatrix}}}}$

According to the above calculation process, the preset brightness of sub-pixel of each color (that is, the maximum brightness after passing through the display screen) can be calculated, the preset brightness of the red sub-pixel is 184.1 nits, the preset brightness of the green sub-pixel is 559.1 nits, and the preset brightness of the blue sub-pixel is 56.8 nits. The preset brightness of white light in the above calculation is 800 nits, which is the maximum brightness considering the overall transmittance of the display screen of the display device including the array substrate. Therefore, the preset brightness of sub-pixel of each color is also the maximum brightness considering the overall transmittance of the display screen.

For example, in the second example of the embodiments of the present disclosure, the preset brightness of white light can be set to 800 nits, and the preset white balance coordinate of white light can be (0.307, 0.321), then the colorimetric value of the object color of white light is (765.1, 800, 927.1).

For example, the central value of the preset color coordinate of the red sub-pixel can be (0.697, 0.303), the central value of the preset color coordinate of the green sub-pixel can be (0.290, 0.68), and the central value of the preset color coordinate of the blue sub-pixel can be (0.132, 0.062). According to the above relationships (8-10) and the relationship (12), the preset brightness of the red sub-pixel is 163.2 nits, the preset brightness of the green sub-pixel is 567.4 nits, and the preset brightness of the blue sub-pixel is 69.4 nits.

For example, in the third example of the embodiments of the present disclosure, the preset brightness of white light can be set to 1000 nits, and the preset white balance coordinate of white light can be (0.307, 0.321), and the colorimetric value of the object color of white light is (956.4, 1000, 1158.9).

For example, the central value of the preset color coordinate of the red sub-pixel can be (0.698, 0.302), the central value of the preset color coordinate of the green sub-pixel can be (0.298, 0.662), and the central value of the preset color coordinate of the blue sub-pixel can be (0.137, 0.062). According to the above relationships (8-10) and the relationship (12), the preset brightness of the red sub-pixel is 190.4 nits, the preset brightness of the green sub-pixel is 723.3 nits, and the preset brightness of the blue sub-pixel is 86.3 nits.

S102: Acquiring a preset current efficiency of sub-pixel of each color.

For example, the current efficiency of sub-pixel of each color can be directly measured by an optical testing equipment and an electrical testing equipment. The optical testing device may be, for example, a spectrophotometer PR788, and an electrical testing device may be, for example, a digital source meter Keithley 2400. In the process of designing the channel width-length ratios of the driving transistors of sub-pixels with different colors, the required preset current efficiency can be obtained according to the measured current efficiency of sub-pixel of each color in a general display device. According to different materials of the organic light emitting elements of sub-pixels with different colors, the preset current efficiency of respective organic light emitting elements are also different.

For example, in the first example, the current efficiency of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 48 cd/A, 118 cd/A, and 7.2 cd/A, respectively.

For example, taking the area of the effective display region of the display device including the array substrate in the embodiments of the present disclosure being 0.031981 square meters as an example, the currents required by the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be obtained according to the above relationship (3), and the currents of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 292 mA, 361 mA and 601 mA, respectively. It should be noted that the brightness used in calculating the current is the brightness considering the overall transmittance of the screen. In the embodiments of the present disclosure, the overall transmittance of the display screen is 42%, and the brightness of the red sub-pixel used to calculate the current is 438.3 nits, the brightness of the green sub-pixel used to calculate the current is 1331.2 nits, and the brightness of the blue sub-pixel used to calculate the current is 135.2 nits.

According to the above parameters, assuming that the driving transistors of sub-pixels of respective colors adopt the same channel width-length ratio, the current required to be provided to the blue sub-pixel is 2.06 times the current required to be provided to the red sub-pixel, and the current required to be provided to the blue sub-pixel is 1.67 times the current required to be provided to the green sub-pixel. As a result, the driving transistor of the blue sub-pixel may not be able to provide such a large current because of insufficient driving capability, resulting in insufficient brightness of blue light of the display device, thereby affecting the white balance of white light.

For example, in the second example, the current efficiency of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 24 cd/A, 98 cd/A, and 5.8 cd/A, respectively.

For example, taking the area of the effective display region of the display device including the above array substrate being 0.031981 square meters as an example, according to the above relationship (3), the required currents of the red sub-pixel, the green sub-pixel and the blue sub-pixel can be obtained, and the required currents are 518 mA, 441 mA, and 911 mA, respectively.

According to the above parameters, assuming that the driving transistors of sub-pixels of respective colors adopt the same channel width-length ratio, the current required to be provided to the blue sub-pixel is 1.76 times the current required to be provided to the red sub-pixel and 2.06 times the current required to be provided to the green sub-pixel. As a result, the driving transistor of the blue sub-pixel may not be able to provide such a large current because of insufficient driving capability, resulting in insufficient brightness of blue light of the display device, thereby affecting the white balance of white light.

For example, in the third example, the current efficiency of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 30 cd/A, 118 cd/A, and 8 cd/A, respectively.

For example, taking the area of the effective display region of the display device including the above array substrate being 0.031981 square meters as an example, the required currents of the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be obtained according to the above relationship (3), and the required currents are 483 mA, 467 mA, and 821 mA, respectively.

According to the above parameters, assuming that the driving transistors of sub-pixels of respective colors adopt the same channel width-length ratio, the current required to be provided to the blue sub-pixel is 1.7 times the current required to be provided to the red sub-pixel and 1.76 times the current required to be provided to the green sub-pixel. As a result, the driving transistor of the blue sub-pixel may not be able to provide such a large current because of insufficient driving capability, resulting in insufficient brightness of blue light of the display device, thereby affecting the white balance of white light.

In the embodiments of the present disclosure, the channel width-length ratio of the driving transistor of the blue sub-pixel is designed to be larger than the channel width-length ratios of the driving transistors of the sub-pixels with other colors, so that the driving transistor of the blue sub-pixel can provide the current value required for the maximum brightness or the highest gray level of the blue sub-pixel, so that the brightness of white light can reach 800 nits or more while ensuring that the white light of the display device is in the preset white balance color coordinate state.

S103: calculating a ratio of channel width-length ratios of driving transistors of sub-pixels of respective colors according to the preset brightness and the preset current efficiency of sub-pixels of respective colors.

For example, the preset current efficiency of the first color sub-pixel is E1, the preset current efficiency of the second color sub-pixel is E2, the preset brightness of the first color sub-pixel is Y1, and the preset brightness of the second color sub-pixel is Y2. According to the preset brightness and the preset current efficiency of the first color sub-pixel and the second color sub-pixel, a step of calculating the ratio of the channel width-length ratio of the first driving transistor to the channel width-length ratio of the second driving transistor includes: setting the channel width-length ratio of the first driving transistor to be W1/L1, and the channel width-length ratio of the second driving transistor to be W2/L2; acquiring the preset data signal Vdata1 input to the first color sub-pixel, and the preset data signal Vdata2 input to the second color sub-pixel, and the preset power supply voltage Vdd input to sub-pixel of each color; and calculating the ratio according to the ratio relationship of (W1/L1):(W2/L2) that the ratio of the channel width-length ratio of the first driving transistor and the channel width-length ratio of the second driving transistor substantially satisfies.

For example, the preset current efficiency of the blue sub-pixel, the preset current efficiency of the red sub-pixel, and the preset current efficiency of the green sub-pixel are E_(B), E_(R), and E_(G), respectively, and the preset brightness of the blue sub-pixel, the preset brightness of the red sub-pixel, and the preset brightness of the green sub-pixel are Y_([B]), Y_([R]) and Y_([G]), respectively.

For example, the ratio of the channel width-length ratios of the driving transistors of sub-pixels of respective colors can be calculated according to the above parameters and the relationship (5). Assuming that the preset data signal Vdata input to sub-pixel of each color is the same, and in a case where the brightness of sub-pixel of each color is at the highest brightness or the highest gray level of the display device, the channel width-length ratios of the driving transistors in the red sub-pixel, the green sub-pixel and the blue sub-pixel satisfy the following ratio relationship (13):

(W/L)_(R):(W/L)_(G):(W/L)_(B)=(Y _([R]) /E _(R)):(Y _([G]) /E _(G)):(Y _([B]) /E _(B)).

Substituting the parameters in the first example into the relationship (13), it can be obtained:

(W/L)_(R):(W/L)_(G):(W/L)_(B)=1:1.24:2.06.

Substituting the parameters in the second example into the relationship (13), it can be obtained:

(W/L)_(R):(W/L)_(G):(W/L)_(B)=1:0.85:1.76.

Substituting the parameters in the third example into the relationship (13), it can be obtained:

(W/L)_(R):(W/L)_(G):(W/L)_(B)=1:0.97:1.7.

In the actual display process, the difference of the data signals input to sub-pixels of respective colors can be designed to be small (for example, the difference of the data signals input to the sub-pixels with different colors is not greater than 1.5V), so that sub-pixels of respective colors have substantially the same data signal range.

Considering the disparity in actual process capability, the ratio of the channel width-length ratios of the driving transistors in the red sub-pixel, the green sub-pixel and the blue sub-pixel can be set to 1:1:2. The embodiments of the present disclosure are not limited thereto, as long as the ratio of the channel width-length ratios of the driving transistors of the red sub-pixel, the green sub-pixel, and the blue sub-pixel satisfies the range of 1:(0.7-1.3):(1.5-2.5).

For example, the channel width-length ratio of the driving transistor of the blue sub-pixel can be designed to be 5/25, and the channel width-length ratios of the green sub-pixel and the red sub-pixel are designed to be 3/30 according to the ratio relationship of the channel width-length ratios of the driving transistors of the above sub-pixels with different colors. The embodiments of the present disclosure are not limited thereto, and the ratios can be adjusted according to actual process requirements. For example, the channel width-length ratio of the driving transistor of the blue sub-pixel can be designed to be in a range of 4/25-6.5/25, and the channel width-length ratio of the green sub-pixel and the red sub-pixel are both designed to be in a range of 2.4/30-4/30 according to the ratio relationship of the channel width-length ratios of the driving transistors of the above sub-pixels with different colors.

FIG. 3 is a simulation curve of a data voltage input to sub-pixel of each color and a current flowing between the drain electrode and the source electrode of a thin film transistor for driving an organic light emitting element of sub-pixel of each color in the second example of embodiments of the present disclosure. According to the ratio relationship of the channel width-length ratios of the driving transistors of the sub-pixels in the second example (that is, (W/L)_(R):(W/L)_(G):(W/L)_(B)≈1:1:2), the channel width-length ratio of the driving transistor of sub-pixel of each color is set, thereby obtaining the simulation curve shown in FIG. 3. As shown in FIG. 3, assuming that the effective display area of the display device is 0.031981 m² and the resolution is 1920*720, in a case where the preset data voltage input to sub-pixel of each color is −2.118V, the current flowing between the drain electrode and the source electrode of the thin film transistor for driving the organic light emitting element of the blue sub-pixel is about 666.9 nanoamperes, and the current value required for all blue sub-pixels is 666.9*1920*720 nanoamperes, that is, 921 milliamperes; the current flowing between the drain electrode and the source electrode of the thin film transistor for driving the organic light emitting element of the red sub-pixel is about 322.9 milliamperes, and the current value required for all red sub-pixels is 322.9*1920*720 nanoamperes, that is, 446 milliamperes; and the current flowing between the drain electrode and the source electrode of the thin film transistor for driving the organic light emitting element of the green sub-pixel is about 378.3 milliamperes, and the current value required for all green sub-pixels is 378.3*1920*720 nanoamperes, that is, 523 milliamperes. The result in this simulation curve roughly matches the value of the current required by sub-pixel of each color in the second example. Therefore, by designing the channel width-length ratio of the driving transistor of the blue sub-pixel to be larger than the channel width-length ratios of the driving transistors of the sub-pixels with other colors, the driving transistor of the blue sub-pixel can provide the current value required for the maximum brightness or the highest gray scale of the blue sub-pixel, so that the brightness of white light can reach 800 nits or more while ensuring that the white light is in the white balance state.

FIG. 4 is a curve of gate voltages and currents between the drain electrode and source electrode of driving transistors with different channel width-length ratios. The different curves in FIG. 4 respectively represent different channel width-length ratios. As shown in FIG. 4, in a driving transistor with a channel width-length ratio of 3/35, the threshold voltage of the driving transistor is −2.47094V, and the gate voltage of the driving transistor is −5.9V; in a driving transistor with a channel width-length ratio of 4/35, the threshold voltage of the driving transistor is −2.5126V, and the gate voltage of the driving transistor is −5.9V; and in a driving transistor with a channel width-length ratio of 5/35, the threshold voltage of the driving transistor is −2.4872V, and the gate voltage of the driving transistor is −5.4V. It can be known from the values of the gate voltage and the threshold voltage of each driving transistor that changing the channel width-length ratio of the driving transistor basically does not affect the driving characteristics of the driving transistor.

FIG. 5A-FIG. 5C are relationship diagrams of a channel width-length ratio and a charging rate of a driving transistor in sub-pixel of each color. FIG. 5A shows a change of charging rates of driving transistors with different channel width-length ratios in a case where data signals corresponding to a high gray scale (for example, 255 gray scale), a medium gray scale (for example, 128 gray scale) and a low gray scale (for example, 32 gray scale) are written to the driving circuit of the red sub-pixel. As shown in FIG. 5A, the charging rate in a case where the channel width-length ratio of the driving transistor is 5/35 or 4/35 is larger than the charging rate in a case where the channel width-length ratio of the driving transistor is 3/35. Similarly, FIG. 5B shows a change of charging rates of driving transistors with different channel width-length ratios in a case where data signals corresponding to a high gray scale (for example, 255 gray scale), a medium gray scale (for example, 128 gray scale) and a low gray scale (for example, 32 gray scale) are written to the driving circuit of the green sub-pixel. As shown in FIG. 5B, the charging rate in a case where the channel width-length ratio of the driving transistor is 5/35 or 4/35 is larger than the charging rate in a case where the channel width-length ratio of the driving transistor is 3/35. FIG. 5C shows a change of charging rates of driving transistors with different channel width-length ratios in a case where data signals corresponding to a high gray scale (for example, 255 gray scale), a medium gray scale (for example, 128 gray scale) and a low gray scale (for example, 32 gray scale) are written to the driving circuit of the blue sub-pixel. As shown in FIG. 5C, the charging rate in a case where the channel width-length ratio of the driving transistor is 5/35 or 4/35 is larger than the charging rate in a case where the channel width-length ratio of the driving transistor is 3/35. It can be seen that, in the process of changing the channel width-length ratio of the driving transistor of sub-pixel of each color to meet the ratio relationship, it may be considered to increase the channel width-length ratio (for example, increasing the channel width) to increase the charging rate of the driving transistor, thereby reducing the charging time.

Another embodiment of the present disclosure provides an organic light emitting diode display device, which includes the array substrate as mentioned above.

In some examples, the organic light emitting diode display device is a vehicle mounted display device.

In the embodiments of the present disclosure, by designing the channel width-length ratios of the driving transistors of sub-pixels with different colors to be different, the phenomenon of insufficient brightness of blue light when a high-brightness image is displayed on the display screen of the vehicle display device can be avoided as much as possible.

Of course, the embodiments of the present disclosure are not limited to the organic light emitting diode display device being a vehicle mounted display device, the organic light emitting diode display device may also be any product or component with a display function, such as a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, etc. The embodiments are not limited thereto.

Another embodiment of the present disclosure provides a display substrate. FIG. 6 is a schematic block diagram of a display substrate provided by an embodiment of the present disclosure; FIG. 7 is a schematic diagram of repeating units of a display substrate provided by an embodiment of the present disclosure; and FIG. 8 is a planar diagram of a display substrate provided by an embodiment of the present disclosure.

For example, as shown in FIG. 6-FIG. 7, a display substrate 1000 provided by the embodiments of the present disclosure includes a base substrate 100 and a plurality of repeating units 11 arranged along a first direction (that is, Y direction) and a second direction (that is, X) on the base substrate 100, the first direction intersects the second direction. For example, the first direction is perpendicular to the second direction. Each repeating unit 11 includes a plurality of sub-pixels 22, for example, including a first color sub-pixel 110 and a second color sub-pixel 120. Sub-pixel 22 of each color includes an organic light emitting element 220 and a pixel circuit 221. The pixel circuit 221 is used to drive the organic light emitting element 220 to emit light. The pixel circuit 221 includes a driving circuit 222. The driving circuit 222 of the first color sub-pixel 110 includes a first driving transistor 111, the driving circuit 222 of the second color sub-pixel 120 includes a second driving transistor 121, and a channel width-length ratio of the first driving transistor 111 is greater than a channel width-length ratio of the second driving transistor 121. The embodiments of the present disclosure can improve the brightness of the display device including the display substrate by optimizing the channel width-length ratio of the driving transistors of the sub-pixels with different colors on the display substrate.

The relationship of the channel width-length ratio of the first driving transistor and the channel width-length ratio of the second driving transistor in the embodiment of the present disclosure is the same as the relationship of the channel width-length ratio of the first driving transistor and the channel width-length ratio of the second driving transistor in the embodiment shown in FIG. 1A-FIG. 1E, which is not be repeated here.

For example, the display substrate 1000 may be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel and the like. The display substrate 1000 may be an array substrate.

For example, the base substrate 100 may be a suitable substrate such as a glass substrate, a quartz substrate, a plastic substrate, or the like.

For example, as shown in FIG. 7, each repeating unit 11 further includes a third color sub-pixel 130, and the third color sub-pixel 130 includes a third driving transistor 131, a channel width-length ratio of the third driving transistor 131 is less than the channel width-length ratio of the first driving transistor 111.

The relationship of the channel width-length ratio of the first driving transistor, the channel width-length ratio of the second driving transistor, and the channel width-length ratio of the third driving transistor in the embodiment of the present disclosure is the same as the relationship of the channel width-length ratio of the first driving transistor, the channel width-length ratio of the second driving transistor, and the channel width-length ratio of the third driving transistor in the embodiment shown in FIG. 1A-FIG. 1E, which is not be repeated here.

For example, as shown in FIG. 7, in each repeating unit 11, a pixel circuit of the first color sub-pixel 110, a pixel circuit of the second color sub-pixel 120, and a pixel circuit of the third color sub-pixel 130 are arranged sequentially along the first direction (the direction indicated by the arrow in the Y direction). For example, a column of sub-pixels arranged in the X direction are sub-pixels with the same color.

For example, a region covered by an orthographic projection of the pixel circuit of sub-pixel of each color on the base substrate 100 is substantially within a rectangle (as shown by the dashed frame 1101 in FIG. 10). It should be noted that some signal lines of the pixel circuit include portions located inside the rectangle and portions extending outside the rectangle, so the orthographic projection of the pixel circuit on the base substrate here mainly includes orthographic projections of structures such as various transistors, capacitors and the like on the base substrate and orthographic projections of the portions of each signal line within the rectangle on the base substrate.

For example, the organic light emitting element 220 of each sub-pixel 22 includes a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode. One of the first electrode and the second electrode of the organic light emitting element 220 is electrically connected to the driving transistor. The example shown in FIG. 7-FIG. 9E is described by taking the second electrode of the organic light emitting element being connected to the driving transistor as an example.

For example, as shown in FIG. 8, the pixel circuit 221 further includes a first light emitting control circuit 223 and a second light emitting control circuit 224. The driving circuit 222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current for driving the organic light emitting element 220 to emit light. For example, the first light emitting control circuit 223 is connected to a first terminal of the driving circuit 222 and a first voltage terminal VDD, and is configured to turn on or turn off a connection between the driving circuit 222 and the first voltage terminal VDD, and the second light emitting control circuit 224 is electrically connected to a second terminal of the driving circuit 222 and a first electrode of the organic light emitting element 220, and is configured to turn on or turn off a connection between the driving circuit 222 and the organic light emitting element 220.

For example, as shown in FIG. 8, the pixel circuit 221 further includes a data writing circuit 226, a storage circuit 227, a threshold compensation circuit 228, and a reset circuit 229. The data writing circuit 226 is electrically connected to the first terminal of the drive circuit 222 and is configured to write a data signal into the storage circuit 227 under the control of a scanning signal; the storage circuit 227 is electrically connected to a control terminal of the driving circuit 222 and the first voltage terminal VDD, and is configured to store the data signal; the threshold compensation circuit 228 is electrically connected to the control terminal and a second terminal of the driving circuit 222, and is configured to perform threshold compensation on the driving circuit 222; and the reset circuit 229 is electrically connected to the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220, and is configured to reset the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220 under the control of a reset control signal.

For example, as shown in FIG. 8, the driving circuit 222 includes a driving transistor T1, the control terminal of the driving circuit 222 includes a gate electrode of the driving transistor T1, the first terminal of the driving circuit 222 includes a first electrode of the driving transistor T1, and the second terminal of the driving circuit 222 includes a second electrode of the driving transistor T1.

For example, as shown in FIG. 8, the data writing circuit 226 includes a data writing transistor T2, the storage circuit 227 includes a capacitor C, the threshold compensation circuit 228 includes a threshold compensation transistor T3, the first light emitting control circuit 223 includes a first light emitting control transistor T4, the second light emitting control circuit 224 includes a second light emitting control transistor T5, the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

For example, as shown in FIG. 8, a first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, a second electrode of the data writing transistor T2 is configured to be electrically connected to a data line Vd to receive the data signal, and a gate electrode of the data writing transistor T2 is configured to be electrically connected to a first scanning signal line Ga1 to receive the scanning signal; a first electrode of the capacitor C is electrically connected to the first voltage terminal VDD, and a second electrode of the capacitor C is electrically connected to the gate electrode of the driving transistor T1; a first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, a second electrode of the threshold compensation transistor T3 is electrically connected to the gate electrode of the driving transistor T1, and a gate electrode of the threshold compensation transistor T3 is configured to be electrically connected to a second scanning signal line Ga2 to receive a compensation control signal; a first electrode of the first reset transistor T6 is configured to be electrically connected to a first reset power supply terminal Vinit1 to receive a first reset signal, a second electrode of the first reset transistor T6 is electrically connected to the gate electrode of the driving transistor T1, and a gate electrode of the first reset transistor T6 is configured to be electrically connected to a first reset control signal line Rst1 to receive a first sub-reset control signal; a first electrode of the second reset transistor T7 is configured to be electrically connected to a second reset power supply terminal Vinit2 to receive a second reset signal, a second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organic light emitting element 220, and a gate electrode of the second reset transistor T7 is configured to be electrically connected to a second reset control signal line Rst2 to receive a second sub-reset control signal; a first electrode of the first light emitting control transistor T4 is electrically connected to the first voltage terminal VDD, a second electrode of the first light emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and a gate electrode of the first light emitting control transistor T4 is configured to be electrically connected to a first light emitting control signal line EM1 to receive a first light emitting control signal; a first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, a second electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the organic light emitting element 220, and a gate electrode of the second light emitting control transistor T5 is configured to be electrically connected to a second light emitting control signal line EM2 to receive a second light emitting control signal; and the first electrode of the organic light emitting element 220 is electrically connected to a second voltage terminal VSS.

For example, one of the first voltage terminal VDD and the second voltage terminal VSS is a high voltage terminal and the other of the first voltage terminal VDD and the second voltage terminal VSS is a low voltage terminal. For example, in the embodiment as shown in FIG. 8, the first voltage terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; and the second voltage terminal VSS may be a voltage source to output a constant second voltage, the second voltage is a negative voltage or the like. For example, in some examples, the second voltage terminal VSS may be grounded.

For example, as shown in FIG. 8, the scanning signal may be the same as the compensation control signal, that is, the gate electrode of the data writing transistor T2 and the gate electrode of the threshold compensation transistor T3 may be electrically connected to the same signal line, such as the first scanning signal line Ga1, to receive the same signal (e.g., scanning signal), in this case, the display substrate 1000 may not be provided with the second scanning signal line Ga2, thereby reducing the number of signal lines. For another example, the gate electrode of the data writing transistor T2 and the gate electrode of the threshold compensation transistor T3 may be electrically connected to different signal lines, i.e., the gate electrode of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, the gate electrode of the threshold compensation transistor T3 is electrically connected to the second scanning signal line Ga2, and a signal transmitted by the first scanning signal line Ga1 is the same as a signal transmitted by the second scanning signal line Ga2.

It should be noted that the scanning signal and the compensation control signal may also be different, so that the gate electrode of the data writing transistor T2 and the gate electrode of the threshold compensation transistor T3 can be separately and independently controlled, thereby increasing the flexibility of controlling the pixel circuit.

For example, as shown in 8, the first light emitting control signal may be the same as the second light emitting control signal, that is, the gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 may be electrically connected to the same signal line, such as the first light emitting control signal line EM1, to receive the same signal (e.g., the first light emitting control signal), and in this case, the display substrate 1000 may not be provided with the second light emitting control signal line EM2, thereby reducing the number of signal lines. For another example, the gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 may also be electrically connected to different signal lines, i.e., the gate electrode of the first light emitting control transistor T4 is electrically connected to the first light emitting control signal line EM1, the gate electrode of the second light emitting control transistor T5 is electrically connected to the second light emitting control signal line EM2, and a signal transmitted by the first light emitting control signal line EM1 is the same as a signal transmitted by the second light emitting control signal line EM2.

It should be noted that in a case where the first light emitting control transistor T4 and the second light emitting control transistor T5 are transistors with different types, for example, in a case where the first light emitting control transistor T4 is a P-type transistor and the second light emitting control transistor T5 is an N-type transistor, the first light emitting control signal and the second light emitting control signal may also be different, and the embodiments of the present disclosure are not limited thereto.

For example, the first sub-reset control signal may be the same as the second sub-reset control signal, that is, the gate electrode of the first reset transistor T6 and the gate electrode of the second reset transistor T7 may be electrically connected to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (e.g., the first sub-reset control signal). In this case, the display substrate 1000 may not be provided with the second reset control signal line Rst2, thereby reducing the number of signal lines. For another example, the gate electrode of the first reset transistor T6 and the gate electrode of the second reset transistor T7 may be electrically connected to different signal lines, i.e., the gate electrode of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1, the gate electrode of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and a signal transmitted by the first reset control signal line Rst1 is the same as a signal transmitted by the second reset control signal line Rst2. It should be noted that the first sub-reset control signal and the second sub-reset control signal may also be different.

For example, in some examples, the second sub-reset control signal may be the same as the scanning signal, that is, the gate electrode of the second reset transistor T7 may be electrically connected to the first scanning signal line Ga1 to receive the scanning signal as the second sub-reset control signal.

For example, the source electrode of the first reset transistor T6 and the source electrode of the second reset transistor T7 are connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2, respectively. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be DC reference voltage terminals to output constant DC reference voltages. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be the same, for example, the source electrode of the first reset transistor T6 and the source electrode of the second reset transistor T7 are connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be high voltage terminals or low voltage terminals, as long as the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can provide the first reset signal and the second reset signal to reset the gate electrode of the driving transistor T1 and the second electrode of the organic light emitting element 220, and the present disclosure is not limited thereto.

It should be noted that the driving circuit 222, the data writing circuit 226, the storage circuit 227, the threshold compensation circuit 228, and the reset circuit 229 in the pixel circuit as shown in FIG. 8 are only schematic. The specific structures of the driving circuit 222, the data writing circuit 226, the storage circuit 227, the threshold compensation circuit 228, and the reset circuit 229 can be set according to actual application requirements, and the embodiments of the present disclosure are not specifically limited thereto.

For example, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present disclosure illustrate the technical solution of the present disclosure by taking a case that transistors are P-type transistors (e.g., P-type MOS transistors) as an example, that is, in the descriptions of the present disclosure, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6, the second reset transistor T7, etc. may be P-type transistors. However, the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art may also use N-type transistors (e.g., N-type MOS transistors) to achieve the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors, etc. A source electrode and a drain electrode of a transistor can be symmetrical in structure, so the source electrode and the drain electrode of the transistor can be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish two electrodes of transistors, except for a gate electrode serving as a control electrode, one of the two electrodes is directly described as a first electrode, and the other of the two electrodes is described as a second electrode, so the first electrodes and the second electrodes of all or part of the transistors in the embodiments of the present disclosure are interchangeable as required.

It should be noted that in the embodiments of the present disclosure, in addition to the 7T1C structure as shown in FIG. 8 (i.e., including seven transistors and one capacitor), the pixel circuit of the sub-pixel may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, the embodiments of the present disclosure are not limited thereto.

FIG. 9A-FIG. 10A are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure. The positional relationship of the respective circuits in the pixel circuit on a backplane will be described below with reference to FIG. 9A-FIG. 10A. The example shown in FIG. 9A-FIG. 10A takes pixel circuits 221 of one repeating unit 11 as an example, and the position of each transistor of the pixel circuit in the first color sub-pixel 110 is illustrated, and the components of the pixel circuits in the sub-pixels with other colors are substantially the same as the positions of the transistors in the first color sub-pixel. As shown in FIG. 9A, the pixel circuit 221 of the first color sub-pixel 110 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emitting control transistor T4, and a second light emitting control transistor T5, a first reset transistor T6 and a second reset transistor T7, and a capacitor C, as shown in FIG. 8.

FIG. 9A-FIG. 10A also show the first scanning signal line Ga1, the second scanning signal line Ga2, the first reset control signal line Rst1, the second reset control signal line Rst2, the first reset power signal line Init1 of the first reset power supply terminal Vinit1, the second reset power signal line Init2 of the second reset power supply terminal Vinit2, the first lighting control signal line EM1, the second lighting control signal line EM2, the data line Vd, the first power signal line VDD1 of the first power supply terminal VDD, the second power signal line VDD2, the third power signal line VDD3, and the shielding line 344 that are electrically connected to the pixel circuit 121 of sub-pixel of each color. The first power signal line VDD1 and the second power signal line VDD2 are electrically connected with each other, and the first power signal line VDD1 and the third power signal line VDD3 are electrically connected with each other.

It should be noted that in the example shown in FIG. 9A-FIG. 9E, the first scanning signal line Ga1 and the second scanning signal line Ga2 are the same signal line, the first reset power signal line Intl and the second reset power signal line Init2 are the same signal line, the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line, and the first light emitting control signal line EM1 and the second light emitting control signal line EM2 are the same signal line, but the embodiments are not limited to thereto.

For example, FIG. 9A shows an active semiconductor layer 310 of the pixel circuit in the display substrate. The active semiconductor layer 310 may be patterned using a semiconductor material. The active semiconductor layer 310 may be used to form active layers of the above-mentioned driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7. The active semiconductor layer 310 includes an active layer pattern and a doped region pattern (that is, a source region s and a drain region d shown in the third color sub-pixel) of the transistors of respective sub-pixels, and the active layer pattern and the doped region pattern of respective transistors in the same pixel circuit are provided integrally.

It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region therein may be conductive by doping or the like to realize electrical connection of each structure. That is, the active semiconductor layer of transistors of each sub-pixel is an integrated pattern formed of p-silicon, and each transistor in the same pixel circuit includes doped region patterns (that is, the source region s and the drain region d) and the active layer pattern, and the active layers of different transistors are separated by a doped structure.

For example, the active semiconductor layers in the pixel circuits of the sub-pixels with different colors arranged along the first direction have no connection relationship and are disconnected from each other. The active semiconductor layers in the pixel circuits of sub-pixels of the same color arranged along the second direction may be provided integrally, or may be disconnected from each other.

For example, the active semiconductor layer 310 may be prepared by amorphous silicon, polysilicon, oxide semiconductor material, or the like. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.

For example, a gate electrode metal layer of the pixel circuit may include a first conductive layer and a second conductive layer. A gate insulating layer (as shown in FIG. 10B and FIG. 10C) is formed on the active semiconductor layer 310 to protect the active semiconductor layer 310. FIG. 9B shows a first conductive layer 320 of the display substrate, the first conductive layer 320 is disposed on the gate insulating layer, so as to be insulated from the active semiconductor layer 310. The first conductive layer 320 may include a second electrode CC2 of the capacitor C, the first scanning signal line Ga1, the first reset control signal line Rst1, the first light emitting control signal line EM1, and gate electrodes of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7.

For example, as shown in FIG. 9B, the gate electrode of the data writing transistor T2 may be a portion of the first scanning signal line Ga1 that overlaps with the active semiconductor layer 310, the gate electrode of the first light emitting control transistor T4 may be a first portion of the first light emitting control signal line EM1 that overlaps with the active semiconductor layer 310, the gate electrode of the second light emitting control transistor T5 may be a second portion of the first light emitting control signal line EM1 that overlaps with the active semiconductor layer 310, the gate electrode of the first reset transistor T6 may be a first portion of the first reset control signal line Rst1 that overlaps with the active semiconductor layer 310, the gate electrode of the second reset transistor T7 is a second portion of the first reset control signal line Rst1 that overlaps with the active semiconductor layer 310. The threshold compensation transistor T3 may be a thin film transistor with a double gate structure, a first gate electrode of the threshold compensation transistor T3 may be a portion of the first scanning signal line Ga1 that overlaps with the active semiconductor layer 310, and a second gate electrode of the threshold compensation transistor T3 may be a portion of a protrusion portion protruding from the first scanning signal line Ga1 that overlaps with the active semiconductor layer 310. As shown in FIG. 8 and FIG. 9B, the gate electrode of the driving transistor T1 may be the second electrode CC2 of the capacitor C.

It should be noted that respective dashed rectangular frames in FIG. 9A show respective portions of the first conductive layer 320 that overlap with the active semiconductor layer 310.

For example, as shown in FIG. 9B, the first scanning signal line Ga1, the first reset control signal line Rst1, and the first light emitting control signal line EM1 are arranged along the second direction X. The first scanning signal line Ga1 is located between the first reset control signal line Rst1 and the first light emitting control signal line EM1.

For example, in the second direction X, the second electrode CC2 of the capacitor C (i.e., the gate electrode of the driving transistor T1) is located between the first scanning signal line Ga1 and the first light emitting control signal line EM1. The protrusion portion P protruding from the first scanning signal line Ga1 is located on a side of the first scanning signal line Ga1 away from the first light emitting control signal line EM1.

For example, as shown in FIG. 9A, in the second direction X, the gate electrode of the data writing transistor T2, the gate electrode of the threshold compensation transistor T3, the gate electrode of the first reset transistor T6, and the gate electrode of the second reset transistor T7 are all located on a first side of the gate electrode of the driving transistor T1, the gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 are both located on a second side of the gate electrode of the driving transistor T1. For example, in the example as shown in FIG. 9A-FIG. 10A, the first side and the second side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel are opposite sides of the gate electrode of the driving transistor T1 in the second direction X. For example, as shown in FIG. 9A-FIG. 10A, in the XY plane, the first side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel may be an upper side of the gate electrode of the driving transistor T1, and the second side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel may be a lower side of the gate electrode of the driving transistor T1. For the lower side, for example, the side of the display substrate for bonding an IC is the lower side of the display substrate, and the lower side of the gate electrode of the driving transistor T1 is the side of the gate electrode in the driving transistor T1 close to the IC. The upper side is the opposite side of the lower side, for example, is the side of the gate electrode of the driving transistor T1 away from the IC.

For example, in some embodiments, as shown in FIG. 9A-FIG. 10A, in a first direction Y, the gate electrode of the data writing transistor T2 and the gate electrode of the first light emitting control transistor T4 are both located on a third side of the gate electrode of the driving transistor T1, the first gate electrode of the threshold compensation transistor T3, the gate electrode of the second light emitting control transistor T5, and the gate electrode of the second reset transistor T7 are all located on a fourth side of the gate electrode of the driving transistor T1. For example, in the example shown in FIG. 9A-FIG. 10A, the third side and the fourth side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel are opposite sides of the gate electrode of the driving transistor T1 in the first direction Y. For example, as shown in FIG. 9A-FIG. 10A, the third side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel may be a left side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel, and the fourth side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel may be a right side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel. For the left side and the right side, for example, in the same pixel circuit, the data line is on the left side of the first power signal line VDD1, and the first power signal line VDD1 is on the right side of the data line.

For example, a first insulating layer (as shown in FIG. 10B and FIG. 10C) is formed on the first conductive layer 320 to protect the first conductive layer 320 as mentioned above. FIG. 9C shows a second conductive layer 330 of the pixel circuit. The second conductive layer 330 includes a first electrode CC1 of the capacitor C, the first reset power signal line Init1, the second power signal line VDD2, and a light shielding portion S. The second power signal line VDD2 and the first electrode CC1 of the capacitor C are formed integrally. The first electrode CC1 of the capacitor C and the second electrode CC2 of the capacitor C at least partially overlap with each other to form the capacitor C.

For example, a second insulating layer (as shown in FIG. 10B and FIG. 10C) is formed on the second conductive layer 330 to protect the second conductive layer 330. FIG. 9D shows a source-drain metal layer 340 of the pixel circuit, and the source-drain metal layer 340 includes the data line Vd, the first power signal line VDD1, and the shielding line 334. The abovementioned data line Vd, the first power signal line VDD1, and the shielding line 334 extend along the X direction. The shielding line 344 and the data line Vd are formed in the same layer and have the same material, so that the shielding line and the data line can be formed simultaneously in the same patterning process, thereby avoiding adding an additional patterning process for manufacturing the shielding line, simplifying the manufacturing process of the display substrate, and saving the manufacturing cost.

For example, the source-drain metal layer 340 further includes a first connection portion 341, a second connection portion 342, and a third connection portion 343. FIG. 9D also shows exemplary locations of a plurality of via holes, and the source-drain metal layer 340 is connected to a plurality of film layers between the source-drain metal layer 340 and the base substrate through the plurality of via holes as illustrated. As shown in FIG. 9D, differently filled via holes indicate that the source-drain metal layer 340 is connected to different film layers through the via holes. For example, the source-drain metal layer 340 is connected to the active semiconductor layer 310 shown in FIG. 9A through via holes filled white color, and the source-drain metal layer 340 is connected to the second semiconductor layer shown in FIG. 9C through via holes filled with black dot. The specific film layer where each via hole is located, and the specific connection relationship of each via hole will be described in detail in the subsequent drawing shown in FIG. 10A.

For example, a third insulating layer and a fourth insulating layer (as shown in FIG. 10B and FIG. 10C) are formed on the above-mentioned source-drain metal layer 340 to protect the source-drain metal layer 340 as mentioned above. The second electrode of the organic light emitting element of each sub-pixel may be on a side of the third insulating layer and the fourth insulating layer away from the base substrate.

FIG. 9E shows a third conductive layer 350 of the pixel circuit, the third conductive layer 350 includes a fourth connection portion 353 and a third power signal line VDD3, and the third power signal line VDD3 is distributed crosswise in the X direction and the Y direction. FIG. 9E also shows exemplary locations of a plurality of via holes 351 and 354, and the third conductive layer 350 is connected to the source-drain metal layer 340 through the plurality of via holes 351 and 354 shown.

FIG. 10A is a schematic diagram of a stacked positional relationship of the above-mentioned active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source-drain metal layer 340, and the third conductive layer 350. As shown in FIG. 9A-FIG. 10A, the data line Vd is connected to the source region of the data writing transistor T2 in the active semiconductor layer 310 through at least one via hole (e.g., the via hole 381) in the gate insulating layer, the first insulating layer, and the second insulating layer. The first power signal line VDD1 is connected to the source region of the first light emitting control transistor T4 in the active semiconductor layer 310 through at least one via hole (e.g., the via hole 382) in the gate insulating layer, the first insulating layer, and the second insulating layer.

As shown in FIG. 9A-FIG. 10A, one terminal of the first connection portion 341 is connected to the drain region of the threshold compensation transistor T3 in the active semiconductor layer 310 through at least one via hole (e.g., the via hole 384) in the gate insulating layer, the first insulating layer, and the second insulating layer, and the other terminal of the first connection portion 341 is connected to the gate electrode of the driving transistor T1 (i.e., the second electrode CC2 of the capacitor C) in the first conductive layer 320 through at least one via hole (e.g., the via hole 385) in the first insulating layer and the second insulating layer. One terminal of the second connection portion 342 is connected to the first reset power signal line Init1 through one via hole (e.g., the via hole 386) in the second insulating layer, and the other terminal of the second connection portion 342 is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310 through at least one via hole (e.g., the via hole 387) in the gate insulating layer, the first insulating layer, and the second insulating layer. The third connection portion 343 is connected to the drain region of the second light emitting control transistor T5 in the active semiconductor layer 310 through at least one via hole (e.g., the via hole 388) in the gate insulating layer, the first insulating layer, and the second insulating layer. It should be noted that the source region and the drain region of the transistor used in the embodiments of the present disclosure may be the same in structure, so the source region and the drain region may be indistinguishable in structure, and are interchangeable according to needs.

As shown in FIG. 9A-FIG. 10A, the first power signal line VDD1 is connected to the first electrode CC1 of the capacitor C through at least one via hole (e.g., the via hole 3832) in the second insulating layer between the second conductive layer 330 and the source-drain metal layer 340.

For example, as shown in FIG. 9A-FIG. 10A, the shielding line 344 extends in the X direction, and an orthographic projection of the shielding line 344 on the base substrate is located between an orthographic projection of the driving transistor on the base substrate and an orthographic projection of the data line on the base substrate. For example, the shielding line in the pixel circuit of the first color sub-pixel can reduce the influence of the signal transmitted on the data line in the pixel circuit of the second color sub-pixel on the performance of the threshold compensation transistor T3 of the first color sub-pixel, thereby reducing the influence of the coupling between the gate electrode of the driving transistor of the first color sub-pixel and the data line connecting the second color sub-pixel, and reducing the crosstalk problem.

For example, as shown in FIG. 9A-FIG. 10A, the shielding line 344 is connected to the first reset power signal line Init1 through at least one via hole in the second insulating layer (e.g., the via hole 332), in addition to allowing the shielding line to have a fixed potential, it also allow the voltage of the initialization signal transmitted on the first reset power signal line to be more stable, which is more conducive to the working performance of the pixel driving circuit.

For example, as shown in FIG. 9A-FIG. 10A, the shielding line 344 is respectively coupled to two first reset power signal lines Init1 extending in the Y direction, so that the shielding line 344 has a fixed potential, and the two first reset power signal lines Init1 are located on two sides of the shielding line 344 along the X direction. For example, the two first reset power signal lines correspond to the n-th row of pixel circuits and the (n+1)-th row of pixel circuits, respectively.

For example, the shielding line 344 in the same column may be an entire shielding line, and the entire shielding line includes a plurality of sub-portions between two adjacent first reset power signal lines, and each sub-portion is located within each pixel circuit region in the column.

For example, in addition to coupling the shielding line 344 to the reset power signal line, the shielding line 344 may also be coupled to the first power signal line, so that the shielding line 344 has the same fixed potential as the power signal transmitted by the first power signal line.

For example, the orthographic projection of the shielding line 344 on the base substrate is between the orthographic projection of the threshold compensation transistor T3 on the base substrate and the orthographic projection of the data line Vd on the base substrate, so that the shielding line 344 can reduce the influence of the change of the signal transmitted on the data line on the performance of the threshold compensation transistor T3, thereby reducing the coupling between the gate electrode of the driving transistor and the data signal line Vd(n+1), thereby solving the problem of vertical crosstalk, and making the display substrate have a better display effect while displaying.

For example, the orthographic projection of the shielding line 344 on the base substrate may be located between the orthographic projection of the first connection portion 341 on the base substrate and the orthographic projection of the data line on the base substrate; and the orthographic projection of the shielding line 344 on the base substrate is located between the orthographic projection of the driving transistor T1 on the base substrate and the orthographic projection of the data line on the base substrate.

The above arrangement greatly reduces the first crosstalk generated between the data line and the threshold compensation transistor, and greatly reduces the second crosstalk generated between the data line and the first connection portion, thereby reducing the indirect crosstalk to the driving transistor caused by the first crosstalk and the second crosstalk. In addition, the above arrangement also reduces the direct crosstalk generated between the data line and the driving transistor, thereby better ensuring the working performance of the display substrate.

For example, the shielding line 344 is not limited to the above-mentioned arrangement, and the shielding line 344 may also be coupled only to the reset power signal line corresponding to the n-th row of pixel circuits, or only to the reset power signal line corresponding to the (n+1)-th row of pixel circuits. Moreover, the extending length of the shielding line 344 in the X direction can also be set according to actual needs.

For example, the pixel circuit of sub-pixel of each color further includes a light shielding portion S1, the light shielding portion S1 is provided in a different layer from the shielding line 344, and an orthographic projection of the shielding portion S1 on the base substrate overlaps with the orthographic projection of the shielding line 344 on the base substrate. The shielding line 344 is connected to the light shielding portion S1 in the second conductive layer 330 through the via hole 331 in the second insulating layer, so that the light shielding portion S1 has a fixed potential, thereby better reducing coupling effect between the threshold compensation transistor T3 and other conductive patterns nearby, and making the working performance of the display substrate more stable.

For example, the light shielding portion S1 overlaps with the active semiconductor layer 310 between the two gate electrodes of the threshold compensation transistor T3, so as to prevent the active semiconductor layer 310 between the two gate electrodes from being irradiated by light to change characteristics, for example, prevent the voltage of the active semiconductor layer 310 between the two gate electrodes from changing, thereby preventing crosstalk.

The example schematically shows that the light shielding portion is connected to the shielding line, but the embodiments are not limited thereto, and the light shielding portion and the shielding line may not be connected.

For example, as shown in FIG. 9A-FIG. 10A, the third power signal line VDD3 is connected to the first power signal line VDD1 through at least one via hole 351 in the third insulating layer and the fourth insulating layer, and the fourth connection portion 353 is connected to the third connection portion 343 through the via hole 354 in the third insulating layer and the fourth insulating layer.

For example, the third insulating layer may be a passivation layer, the fourth insulating layer may be a first planarization layer, and the third insulating layer is located between the fourth insulating layer and the base substrate. The fourth insulating layer may be an organic layer, and the thickness of the organic layer is thicker than that of the inorganic layer such as the passivation layer.

For example, the via hole 351 and the via hole 354 are nested via holes, that is, the via hole 351 includes a first via hole in the third insulating layer and a second via hole in the fourth insulating layer, and the position of the first via hole in the third insulating layer corresponds to the position of the second via hole in the fourth insulating layer, and the orthographic projection of the second via hole in the fourth insulating layer on the base substrate is located in the orthographic projection of the first via hole in the third insulating layer on the base substrate.

For example, the third power signal line VDD3 is distributed in a grid shape, and includes a portion extending in the X direction and a portion extending in the Y direction. The orthographic projection of the portion of the third power signal line VDD3 extending in the X direction on the base substrate substantially coincides with the orthographic projection of the first power signal line VDD1 on the base substrate, or the orthographic projection the first power signal line VDD1 on the base substrate is located in the orthographic projection of the portion of the third power signal line VDD3 extending in the X direction on the base substrate (FIG. 10A shows the example in which the two orthographic projections substantially coincides with each other), and the third power signal line VDD3 and the first power signal line VDD1 are electrically connected, so as to reduce the voltage drop of the first power signal line VDD1, thereby improving the uniformity of the display device.

For example, the third power signal line VDD3 may adopt the same material as the source-drain metal layer.

In order to clearly illustrate each via hole, FIG. 10A does not illustrate the positional relationship between the via hole and each layer.

For example, as shown in FIG. 9A-FIG. 10A, an example of the present disclosure takes a case that relative positional relationships of the components included in the pixel circuits in the first color sub-pixel 110 and the third color sub-pixel 130 are the same as an example, for example, a case that the fourth connection portions 353 of the first color sub-pixel 110 and the third color sub-pixel 130 respectively overlap with the drain regions of the second light emitting control transistors T5 included in respective sub-pixels is taken as an example. The fourth connection portion 353 in the pixel circuit of the second color sub-pixel 120 (for example, the red sub-pixel) does not overlap with the drain region of the second light emitting control transistor T5, for example, the fourth connection portion 353 of the second color sub-pixel 120 and the drain region of the second light emitting control transistor T5 are located on two sides of the third power signal line VDD3 extending in the Y direction, respectively. For example, as shown in FIG. 9D, the third connection portions 343 of the first color sub-pixel and the third color sub-pixel are both in a block structure, and the third connection portion 343 of the second color sub-pixel is a strip portion extending in the X direction. One end of the strip portion is used to connect to the fourth connection portion 353 to be formed later, and the other end of the strip portion is used to connect to the drain region of the second light emitting control transistor T5, so as to connect the fourth connection portion with the drain region of the second light emitting control transistor T5. Then, the anode of sub-pixel of each color formed later will be connected to the corresponding fourth connection portion 353 through a via hole to realize connection between the anode and the drain region of the second light emitting control transistor T5.

The embodiment includes but is not limited thereto. The position of the fourth connection portion in sub-pixel of each color is determined according to the arrangement rule of the organic light emitting elements and the position of the light emitting region.

FIG. 10B is a partial cross-sectional structure diagram taken along the line AA′ shown in FIG. 10A. As shown in FIG. 10A-FIG. 10B, the gate insulating layer 103 is provided on a side of the second electrode (for example, the drain electrode T5 d) of the second light emitting control transistor T5 in the active semiconductor layer in the pixel circuit of the second color sub-pixel 120 away from the base substrate 100. The first light emitting control signal line EM1 is provided on a side of the gate insulating layer 103 away from the base substrate 100, the first insulating layer 104 is provided on a side of the first light emitting control signal line EM1 away from the base substrate 100, the second power signal line VDD2 is provided on a side of the first insulating layer 104 away from the base substrate 100, the second insulating layer 105 is provided on a side of the second power signal line VDD2 away from the base substrate 100, and the third connection portion 343 is provided on a side of the second insulating layer 105 away from the base substrate 100. The third connection portion 343 of the second color sub-pixel 120 is connected to the second electrode T5 d of the second light emitting control transistor T5 in the active semiconductor layer 310 through the via hole 352 in the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105. The third connection portion 343 overlaps with the second power signal line VDD2 and the first light emitting control signal line EM1. The third insulating layer 106 and the fourth insulating layer 107 are provided in sequence on a side of the third connection portion 343 away from the base substrate 100, and the fourth connection portion 353 and the third power signal line VDD3 are provided on a side of the fourth insulating layer 107 away from the base substrate 100. The third power signal line VDD3 overlaps with the second power signal line VDD2. The fourth connection portion 353 is connected to the third connection portion 343 through the nested via hole 354 in the third insulating layer 106 and the fourth insulating layer 107, and thus is connected to the second light emitting control transistor.

For example, as shown in FIG. 10B, the data line Vd is connected to the source electrode T2 s of the data writing transistor T2 through the via hole 381 in the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105; one end of the first connection portion 341 is connected to the drain electrode T3 d of the threshold compensation transistor T3 through the via hole 384 in the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105, and the other end of the first connection portion 341 is connected to the gate electrode of the driving transistor T1 (that is, the second electrode CC2 of the capacitor C) through the via hole 385 in the first insulating layer 104 and the second insulating layer 105; the channel T1 c of the driving transistor T1 is located on a side of the gate electrode facing the base substrate 100, and the channel T1 c does not overlap with the via hole 385, the source electrode T1 d of the driving transistor T1 overlaps with the gate electrode of the driving transistor T1 and the first electrode CC1 of the capacitor C.

FIG. 10C is a partial cross-sectional structure diagram taken along the line B-B′ shown in FIG. 10A. As shown in FIG. 10A-FIG. 10C, The first color sub-pixel 110 is different from the second color sub-pixel 120 in that the orthographic projection of the fourth connection portion 353 in the second color sub-pixel 120 on the base substrate 100 does not overlap with the orthographic projection of the second electrode T5 d of the second light emitting control transistor T5 of the second color sub-pixel 120 on the base substrate 100, and the orthographic projection of the fourth connection portion 353 of the first color sub-pixel 130 on the base substrate 100 overlaps with the orthographic projection of the second electrode T5 d of the second light emitting control transistor T5 of the first color sub-pixel 130 on the base substrate 100. In the first color sub-pixel 110, the third connection portion 343 does not overlap with the second power signal line VDD2 and the first light emitting control signal line EM1. In the first color sub-pixel 110, the channel T1 c of the driving transistor T1 is located on a side of the gate electrode of the driving transistor T1 facing the base substrate 100, and the channel T1 c of the driving transistor T1 overlaps with the via hole 385. It can be seen that the channel width of the driving transistor in the first color sub-pixel is greater than the channel width of the driving transistor in the second color sub-pixel.

For example, as shown in FIG. 9A-FIG. 10A, in the second direction X, the first scanning signal line Ga1, the first reset control signal line Rst1, and the first reset power signal line Init1 are all located on the first side of the gate electrode of the driving transistor T1 in the pixel circuit of the first color sub-pixel, and the first light emitting control signal line EM1 is located on the second side of the driving transistor T1 in the pixel circuit of the first color sub-pixel.

For example, the first scanning signal line Ga1, the first reset control signal line Rst1, the first light emitting control signal line EM1, and the first reset power signal line Init1 all extend in the first direction Y, and the data line Vd extends in the second direction X.

For example, the first power signal line VDD1 extends in the second direction X, and the second power signal line VDD2 extends in the first direction Y. Signal lines connecting the first power supply terminal VDD are routed in grid on the display substrate. In other words, on the entire display substrate, the first power signal line VDD1 and the second power signal line VDD2 are arranged in grid, so that the resistance of the signal lines connecting the first power supply terminal VDD is small, and the voltage drop is low, thereby improving the stability of the power supply voltage provided by the first power supply terminal VDD.

It should be noted that the positional arrangement of the driving circuit, the first light emitting control circuit, the second light emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit in each pixel circuit is not limited to the example shown in FIG. 9A-FIG. 10A, according to actual application requirements, the position arrangement of the driving circuit, the first light emitting control circuit, the second light emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit can be specifically provided.

FIG. 11A is a partial structural diagram of an array substrate provided by an example of the embodiment. As shown in FIG. 11A, the pixel circuit included in sub-pixel of each color in the array substrate of the example is the pixel circuit shown in FIG. 10A. For example, as shown in FIG. 9A-FIG. 11A, a fifth insulating layer (not shown) is provided on a side of the third power signal line VDD3 away from the first power signal line VDD1. For example, the fifth insulating layer may be a second planarization layer, and the material of the fifth insulating layer may be the same as the material of the fourth insulating layer (that is, the first planarization layer), such as an organic material.

For example, as shown in FIG. 9A-FIG. 11A, the second electrode 113 (that is, the anode) of the organic light emitting element of the first color sub-pixel 110 is connected to the fourth connection portion 353 through a via hole (not shown) in the fifth insulating layer, and thus the second electrode is connected to the drain region of the second light emitting control transistor T5. Similarly, the second electrode 133 (that is, the anode) of the organic light emitting element of the third color sub-pixel 130 is connected to the fourth connection portion 353 through a via hole (not shown) in the fifth insulating layer, and thus the second electrode is connected to the drain region of the second light emitting control transistor T5. The second electrode 123 (that is, the anode) of the organic light emitting element of the second color sub-pixel 120 is connected to the fourth connection portion 353 through a via hole in the fifth insulating layer, and thus the second electrode is connected to the third connection portion 343 to realize the connection between the second electrode and the drain region of the second light emitting control transistor T5.

For example, as shown in FIG. 11A, the second electrode of the organic light emitting element of sub-pixel of each color includes a main electrode and a connection electrode, and the main electrode of sub-pixel of each color has a shape of a hexagon.

For example, as shown in FIG. 11A, the second electrode 113 of the first color sub-pixel 110 includes a first main electrode 1131 and a first connection electrode 1132. The first main electrode 1131 and the first connection electrode 1132 may be an integral structure, the first connection electrode 1132 is connected to the fourth connection portion 353 through a connection hole 1133, and thus the first connection electrode is connected to the third connection portion 343 to realize connection between the first connection electrode and the second electrode of the second light emitting control transistor T5 of the first color sub-pixel 110. The second electrode 123 of the second color sub-pixel 120 includes a second main electrode 1231 and a second connection electrode 1232. The second main electrode 1231 and the second connection electrode 1232 may be an integrated structure, and the second connection electrode 1232 is connected to the fourth connection portion 353 through a connection hole 1233, and thus the second connection electrode is connected to the third connection portion 343 to realize connection between the second connection electrode and the second electrode of the second light emitting control transistor T5 of the second color sub-pixel 120. The second electrode 133 of the third color sub-pixel 130 includes a third main electrode 1331 and a third connection electrode 1332. The third main electrode 1331 and the third connection electrode 1332 may be an integrated structure, and the third connection electrode 1332 is connected to the fourth connection portion 353 through a connection hole 1333, and thus the third connection electrode is connected to the third connection portion 343 to realize connection between the third connection electrode and the second electrode of the second light emitting control transistor T5 of the third color sub-pixel 130.

For example, the first connection electrode 1132 of the first color sub-pixel 110 is located on a side of a center of the first main electrode 1131 away from the data line connecting the pixel circuit of the first color sub-pixel in the Y direction, and is located on a side of the center of the first main electrode 1131 away from the light emitting control signal line connecting the pixel circuit of the first color sub-pixel in the X direction. For example, the first connection electrode 1132 and the first main electrode 1131 of the first color sub-pixel 110 are arranged in the X direction, and the first connection electrode 1132 is located on a lower right corner of the first main electrode 1131. For example, the second connection electrode 1232 of the second color sub-pixel 120 is located on a side of a center of the second main electrode 1231 away from the data line connecting the pixel circuit of the second color sub-pixel in the Y direction, and is located on a side of the center of the second main electrode 1231 close to light emitting control signal line of the second color pixel circuit of the sub-pixel in the X direction. For example, the second connection electrode 1232 and the second main electrode 1231 of the second color sub-pixel 120 are arranged in the X direction, and the second connection electrode 1232 is located on a lower right corner of the second main electrode 1231. For example, the third connection electrode 1332 and the third main electrode 1331 of the third color sub-pixel 130 are arranged in the Y direction, and the third connection electrode 1332 is located on the right side of the third main electrode 1331, that is, the third connection electrode 1332 is on a side of the center of the third main electrode close to the shielding line connecting the pixel circuit of the sub-pixel.

For example, a pixel defining layer (such as the pixel defining layer 101 shown in FIG. 1B) is further provided between adjacent sub-pixels. The pixel defining layer includes openings for defining light emitting regions of sub-pixels with different colors. An orthographic projection of an edge of one opening of the pixel defining layer on the base substrate is in an orthographic projection of the main electrode of a corresponding second electrode on the base substrate.

For example, sub-pixel of each color further includes an organic light emitting layer (such as the organic light emitting layer 112 or 122 shown in FIG. 1B), and the organic light emitting layer is located on a side of the second electrode away from the base substrate. The second electrode of sub-pixel of each color is in contact with the organic light emitting layer at the opening of the pixel defining layer, and the opening of the pixel defining layer defines the shape of the light emitting region of the sub-pixel. For example, the second electrode (that is, the anode) of the organic light emitting element may be disposed under the pixel defining layer, and the pixel defining layer includes the opening for defining a sub-pixel, the opening exposes a part of the second electrode, in a case where the organic light emitting layer is formed in the opening of the pixel defining layer, the organic light emitting layer is in contact with the second electrode, and this part can drive the organic light emitting layer to emit light.

For example, the orthographic projection of the opening of the pixel defining layer on the base substrate is in the orthographic projection of the corresponding organic light emitting layer on the base substrate, that is, the organic light emitting layer covers the opening of the pixel defining layer. For example, the area of the organic light emitting layer is larger than the area of the corresponding opening of the pixel defining layer, that is, the organic light emitting layer includes at least a portion covering the physical structure of the pixel defining layer in addition to the portion in the opening of the pixel defining layer, and generally, the organic light emitting layer covers the physical structure of the pixel defining layer at each boundary of the opening of the pixel defining layer. It should be noted that the above description of the organic light emitting layer pattern is based on, for example, the patterned organic light emitting layer of each sub-pixel formed by the FMM process. In addition to the FMM manufacturing process, some organic light emitting layers may be an integral film layer formed by the open mask process on the entire display region, and the orthographic projection of the shape of the integral film layer on the base substrate is continuous, so there must be a portion located in the opening of the pixel defining layer and a portion located on the physical structure of the pixel defining layer.

FIG. 11B is a schematic diagram of the arrangement of the pixels shown in FIG. 11A. As shown in FIG. 11A, the second electrode of the organic light emitting element of sub-pixel of each color has the shape of a hexagon. The plurality of sub-pixels may be divided into a plurality of pixel unit groups 10 arranged in an array in the X direction and the Y direction. Each pixel unit group 10 includes two columns of sub-pixels arranged along the Y direction, and each column of sub-pixels includes a first color sub-pixel 110, a second color sub-pixel 120, and a third color sub-pixel 130. Along the X direction, the two columns of sub-pixels in each pixel unit group 10 are shifted from each other by a distance less than one sub-pixel pitch, for example, the two columns of sub-pixels in each pixel unit group 10 are shifted from each other by about half the pitch of a sub-pixel. For example, the sides of two adjacent sub-pixels facing each other are substantially parallel. For example, the arrangement order of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel in the adjacent column is the same. For example, in the X (column) direction, for example, the first color sub-pixel is located between the second color sub-pixel and the third color sub-pixel that are in a column adjacent to a column of the first color sub-pixel, and the second color sub-pixel is located between the first color sub-pixel and the third color sub-pixel that are in a column adjacent to a column of the second color sub-pixel, and the third color sub-pixel is located between the first color sub-pixel and the second color sub-pixel that are in a column adjacent to a column of the third color sub-pixel.

For example, in one pixel unit group 10, one first color sub-pixel in the first column and one second color sub-pixel and one third color sub-pixel in the second column that are adjacent to the one first color sub-pixel in the first column constitute one pixel unit, which can realize one pixel display. In one pixel unit group 10, among two adjacent pixel units, the first column of sub-pixels and the second column of sub-pixels in the first pixel unit are swapped with the first column and the second column in the second pixel unit, for example, the first color sub-pixel in the first pixel unit is located in the first column, the second color sub-pixel and the third color sub-pixel in the first pixel unit are located in the second column, and the first color sub-pixel in the second pixel unit is located in the second column, and the second color sub-pixel and the third color sub-pixel in the second pixel unit are located in the first column. For example, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel. Each pixel unit includes one blue sub-pixel in one column and one red sub-pixel and one green sub-pixel in the adjacent column that are adjacent to the blue sub-pixel.

For example, the area of the light emitting region of one blue sub-pixel is larger than the area of the light emitting region of one red sub-pixel or the area of the light emitting region of one green sub-pixel. For example, the area of the anode of one blue sub-pixel is larger than the area of the anode of one red sub-pixel or the area of the anode of one green sub-pixel. For example, the main electrode of the anode of the first color sub-pixel and the shape of the main electrode of the anode of the third color sub-pixel have a shape of a roughly regular hexagon, and the shape of the main electrode of the anode of the second color sub-pixel is non-regular hexagon shape and includes two symmetry axes, and a size of the symmetry axis in the X direction is larger than a size of the symmetry axis in the Y direction.

For example, as shown in FIG. 11A, the first main electrode 1131 of the second electrode 113 of the first color sub-pixel 110 covers the driving transistor of the first color sub-pixel 110, the second main electrode 1231 of the second electrode 123 of the second color sub-pixel 120 substantially does not overlap or partially overlap with the driving transistor of the second color sub-pixel 120, and the third main electrode 1331 of the second electrode 133 of the third color sub-pixel 130 does not overlap with the driving transistor of the third color sub-pixel 130.

For example, as shown in FIG. 11A, the first main electrode 1131 of the first color sub-pixel 110 (e.g., the blue sub-pixel) overlaps with the scanning signal line and the light emitting control signal line; the second main electrode 1231 of the second color sub-pixel 120 (e.g., the red sub-pixel) overlaps with the scanning signal line and the reset control signal line; and the third main electrode 1331 of the third color sub-pixel 130 (e.g., the green sub-pixel) overlaps with the light emitting control signal line, the reset control signal line connecting the next row of pixel circuits and the reset power signal line connecting the next row of the pixel circuits. For example, the third main electrode 1331 of the third color sub-pixel 130 (e.g., the green sub-pixel) overlaps with a region of the pixel circuit of the first color sub-pixel (e.g., the blue sub-pixel), in the next row, adjacent to the third color sub-pixel 130.

For example, the first main electrode 1131 of the first color sub-pixel 110 overlaps with a portion of the driving transistor of the third color sub-pixel 130 adjacent to the first color sub-pixel, and the first main electrode 1131 of the first color sub-pixel 110 overlaps with the data line and the shielding line connecting the pixel circuit of the first color sub-pixel 110, and the data line connecting the pixel circuit of the second color sub-pixels 120 adjacent to the first color sub-pixel. The second main electrode 1231 of the second color sub-pixel 120 does not overlap with the data line connecting the pixel circuit of the second color sub-pixel 120, and overlaps with the first power signal line connecting the pixel circuit of the second color sub-pixel 120, the first power signal line and the data line connecting the pixel circuit of the third color sub-pixel 130 adjacent to the second color sub-pixel. The third main electrode 1331 of the third color sub-pixel 130 overlaps with the data line and the first power signal line connecting the pixel circuit of the third color sub-pixel 130, and the first power signal line connecting the pixel circuit of the second color sub-pixel 120 adjacent to the third color sub-pixel.

For example, as shown in FIG. 11A, a side of the first main electrode 1131 of the first color sub-pixel 110 close to the reset control signal line connecting the sub-pixels in the next row is provided with the first connection electrode 1132 connected to the first main electrode 1131; a side of the second main electrode 1231 of the second color sub-pixel 120 close to the reset control signal line connecting the sub-pixels in the next row is provided with the second connection electrode 1232 connected to the second main electrode 1231; and a side of the third main electrode 1331 of the third color sub-pixel 130 close to the second light emitting control transistor of the third color sub-pixel 130 is provided with the third connection electrode 1332 connected to the third main electrode 1331.

For example, as shown in FIG. 11A, the first connection electrode 1132 of the first color sub-pixel 110 overlaps with the second electrode of the second light emitting control transistor in the pixel circuit of the first color sub-pixel 110. The second connection electrode 1232 of the second color sub-pixel 120 does not overlap with the second electrode of the second light emitting control transistor in the pixel circuit of the second color sub-pixel 120, and the second electrode of the second light emitting control transistor of the second color sub-pixel 120 overlaps with the third main electrode 1331 of the third color sub-pixel 130. The third connection electrode 1332 of the third color sub-pixel 130 overlaps with the second electrode of the second light emitting control transistor in the pixel circuit of the third color sub-pixel 130.

FIG. 12 is a partial structural diagram of an array substrate provided by another example of the embodiment. As shown in FIG. 12, the pixel circuit included in sub-pixel of each color in the array substrate in this example is different from the pixel circuit shown in FIG. 10 in that the shapes of the third connection portion in the pixel circuit of the second color sub-pixel 120 and the third connection portion of the third color sub-pixel are the same in this example, and relative positional relationships of the third connection portion in the pixel circuit of the second color sub-pixel 120 and the third connection portion of the third color sub-pixel are the same in the example. In addition, in the second color sub-pixel 120 and the third color sub-pixel 130, the fourth connection portion 353 in the pixel circuit is connected to the third connection portion 343 through the connection via hole 354, and the connection via hole 354 is located on a side of the second electrode of the second light emitting control transistor T5 away from the first light emitting control signal line EM1. In the first color sub-pixel 110, the fourth connection portion 353 in the pixel circuit is connected to the third connection portion 343 through the connection via hole 354, and the connection via hole 354 is located on a side of the second electrode of the second light emitting control transistor T5 close to the first light emitting control signal line EM1. For example, the connection via hole 354 overlaps with the first light emitting control signal line EM1. The second connection electrode 1232 of the second electrode 123 of the second color sub-pixel 120 is connected to the fourth connection portion 353 through a second anode connection via hole 1233, and the second anode connection via hole 1233 is located on a side of the connection via hole 354 close to the first light emitting control signal line EM1. The third connection electrode 1332 of the second electrode 133 of the third color sub-pixel 130 is connected to the fourth connection portion 353 through a third anode connection via hole 1333, and the third anode connection via hole 1333 is located on a side of the via hole 354 close to the first light emitting control signal line EM1. The first connection electrode 1332 of the second electrode 113 of the first color sub-pixel 110 is connected to the fourth connection portion 353 through a first anode connection via hole 1133, and the first anode connection via hole 1133 is located on a side of the connection via hole 354 away from the first light emitting control signal line EM1, so that there is a certain distance between the connection electrode of the second electrode of the first color sub-pixel and the main electrode of the second electrode of the third color sub-pixel, so as to prevent the two electrode from overlapping or approaching to each other to cause defects.

For example, as shown in FIG. 12, the second color sub-pixels 120 (for example, the red sub-pixels) and the third color sub-pixels 130 (for example, the green sub-pixel) are alternately arranged in the Y direction, and the first-color sub-pixels 110 (for example, the blue sub-pixels) adjacent to the second color sub-pixels 120 and the third color sub-pixels 130 are also arranged in the Y direction, and a sub-pixel row formed by the second color sub-pixels 120 and the third color sub-pixels 130 and a sub-pixel row formed by the first-color sub-pixels 110 are alternately distributed in the X direction. For example, an area of the main electrode of the second electrode of one first color sub-pixel 110 is larger than an area of the main electrode of the second electrode of one second color sub-pixel 120, and is larger than an area of the main electrode of the second electrode of one third color sub-pixel 130. For example, the area of the main electrode of the second electrode of the third color sub-pixel 130 is larger than the area of the main electrode of the second electrode of the second color sub-pixel 120. For example, a size of the main electrode of the second electrode of one first color sub-pixel 110 in the Y direction is greater than a size of the main electrode of the second electrode of one second color sub-pixel 120 in the Y direction, and is larger than a size of the main electrode of the second electrode of the third color sub-pixel 130 in the Y direction. For example, the size of the main electrode of the second electrode of the first color sub-pixel 110 in the Y direction does not exceed a span of the main electrode of the second electrode of the second color sub-pixel 120 and the main electrode of the second electrode of the third color sub-pixel 130 in the Y direction, that is, the main electrode of the second electrode of the first color sub-pixel 110, the main electrode of the second electrode of the second color sub-pixel 120, and the main electrode of the second electrode of the third color sub-pixel 130 are projected on a straight line along the Y direction, the projection of the main electrode of the second electrode of the first color sub-pixel 110 is located between the farthest two points respectively on the projection of the main electrode of the second electrode of the second color sub-pixel 120 and the projection of the main electrode of the second electrode of the third color sub-pixel 130. For example, a size of the main electrode of the second electrode of one first color sub-pixel 110 in the X direction, a size of the main electrode of the second electrode of the second color sub-pixel 120 in the X direction, and a size of the main electrode of the second electrode of the third color sub-pixel 130 in the X direction are roughly the same. For example, the size of the main electrode of the second electrode of the second color sub-pixel 120 in the X direction and the size of the main electrode of the second electrode of the third color sub-pixel 130 in the X direction are roughly the same, and a ratio of the size of the main electrode of the second electrode of the third color sub-pixel 130 and the size of the main electrode of the second electrode of one first color sub-pixel 110 in the X direction is 0.8-1.2. For example, the connection electrode of the second electrode of the second color sub-pixel 120 and the connection electrode of the second electrode of the third color sub-pixel 130 are located on a side of the main electrodes of the second color sub-pixel and the third color sub-pixel facing the main electrode of the second electrode of the first color sub-pixel 110. For example, the connection electrode of the second electrode of the first color sub-pixel 110 is located between the sub-pixel row formed by the second color sub-pixel 120 and the third color sub-pixel 130 and the sub-pixel row formed by the first color sub-pixel 110, and is closer to a side of the second electrode of the third color sub-pixel 130 away from the second electrode of the second color sub-pixel 120.

For example, in the second color sub-pixel 120 and the third color sub-pixel 130 arranged in the Y direction, the second anode connection via hole 1233 of the second color sub-pixel 120 and the third anode connection via hole 1333 of the third color sub-pixel 130 are located on a straight line extending along the Y direction, and the first anode connection via hole 1133 of the first color sub-pixel 110 adjacent to the second color sub-pixel 120 and the third color sub-pixel 130 is located on a side of the straight line away from the first scanning signal line Ga1. For example, the first anode connection via hole 1133 of the first color sub-pixel 110 and the connection via hole 354 of the second color sub-pixel 120 and the connection via hole 354 of the third color sub-pixel 130 are located on substantially the same straight line extending in the Y direction. The second anode connection via hole 1233 of the second color sub-pixel 120 overlaps with the second electrode of the second light emitting control transistor T5 of the second color sub-pixel 120, and the third anode connection via hole 1333 of the third color sub-pixel 130 overlaps with the second electrode of the second light emitting control transistor T5 of the third color sub-pixel 130. The first anode connection via hole 1133 of the first color sub-pixel 110 is located on a side of the second electrode of the second light emitting control transistor T5 of the first color sub-pixel 110 away from the first light emitting control signal line EM1.

For example, as shown in FIG. 12, the fourth connection portion overlaps with the drain region of the second light emitting control transistor T5 in the pixel circuit of the second color sub-pixel 120. The shape of the fourth connection portion in the pixel circuit of the second color sub-pixel 120 is the same as that of the fourth connection portion of the third color sub-pixel, and relative positional relationship of the fourth connection portion in the pixel circuit of the second color sub-pixel 120 is the same as that of the fourth connection portion of the third color sub-pixel. A length of the fourth connection portion 353 in the pixel circuit of the first color sub-pixel 110 in the X direction is greater than lengths of the fourth connection portions 353 of the sub-pixels with other two colors in the X direction. The fourth connection portion 353 in the pixel circuit of the first color sub-pixel 110 overlaps with the first light emitting control signal line EM1, but the fourth connection portions 353 of the sub-pixels with other two colors do not overlap with the first light emitting control signal line EM1.

For example, as shown in FIG. 12, the display substrate in this example includes a plurality of pixel units 1 arranged in an array along the first direction and the second direction, and one pixel unit 1 includes one first color sub-pixel 110 and one second color sub-pixel 120 and one third color sub-pixel 130 that are adjacent to the one first color sub-pixel 110.

It should be noted that in the above example, the shape, size, and position of the second electrode of each sub-pixel are schematically shown in the drawings. For each sub-pixel, the actual light emitting region is defined by the opening of the pixel defining layer. For example, the pixel defining layer is in a grid structure, which covers the edge of the second electrode (e.g., the anode) of each sub-pixel, and the pixel defining layer includes a plurality of openings, each opening exposes a portion of the second electrode of one sub-pixel, the light emitting layer is formed at least in the plurality of openings, and a first electrode (e.g., the cathode) is formed on a side of the light emitting layer away from the base substrate, and the first electrode and the second electrode corresponding to the opening of each sub-pixel drive the light emitting layer to emit light. For example, a projection of the edge of the opening of the pixel defining layer of each sub-pixel on the base substrate is in a projection of the second electrode of the sub-pixel on the base substrate, so that the arrangement of each sub-pixel, the arrangement of the opening of the pixel defining layer, and the arrangement position of the second electrode are in one-to-one correspondence. For example, the arrangement position of the second electrode of sub-pixel of each color can be in various ways, as shown in FIG. 11A and FIG. 12, and can also be applied to other pixel arrangements. For example, the pixel circuits of respective sub-pixels are arranged in an array of a plurality of rows and a plurality of columns in the X direction and the Y direction. The pixel circuit structure, such as the data line, the power supply line, the capacitor electrode, and the like, of each sub-pixel can be approximately the same except for the size of the driving transistor and the connection electrode structure. For example, along the Y direction, the pixel circuits of respective sub-pixels are arranged in order of the pixel circuit of the first color sub-pixel, the pixel circuit of the second color sub-pixel, and the pixel circuit of the third color sub-pixel, and along the X direction, each row of pixel circuits of the sub-pixels are repeatedly arranged.

The following statements should be noted:

(1) In the accompanying drawings of the embodiments of the present disclosure, the drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).

(2) In case of no conflict, features in one embodiment or in different embodiments can be combined.

What have been described above are only specific implementations of the present disclosure, the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims. 

What is claimed is:
 1. A display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein at least part of the plurality of sub-pixels comprise an organic light emitting element and a pixel circuit for driving the organic light emitting element to emit light, the organic light emitting element comprises a first electrode, a light emitting layer and a second electrode which are stacked, the second electrode of the organic light emitting element is located between the light emitting layer and the base substrate, the second electrode of the organic light emitting element is electrically connected to the pixel circuit, the pixel circuit comprises a plurality of transistors, the plurality of sub-pixels are arranged along a first direction or a second direction, and the first direction is intersected with the second direction; an active semiconductor layer, comprising channels, source regions and drain regions of the plurality of transistors; a first conductive layer, located on a side of the active semiconductor layer away from the base substrate; a second conductive layer, located on a side of the first conductive layer away from the base substrate; a source-drain metal layer, located on a side of the second conductive layer away from the base substrate; and a third conductive layer, located on a side of the source-drain metal layer away from the base substrate, wherein the source-drain metal layer comprises a first power signal line, and the third conductive layer comprises a second power signal line; the display substrate further comprises reset power signal lines, the reset power signal lines comprise a first reset power signal line and a second reset power signal line; the first reset power signal line and the second reset power signal line are electrically connected to the pixel circuit and configured to provide a reset signal; and the first power signal line and the second power signal line are electrically connected to the pixel circuit.
 2. The display substrate according to claim 1, wherein the display substrate further comprises data lines, a data line is electrically connected to the pixel circuit to provide a data signal; at least one pixel circuit comprises a driving transistor, a first light emitting control transistor, a second light emitting control transistor and a first connection portion, the first connection portion is located in the source-drain metal layer, a first electrode of the first light emitting control transistor is electrically connected to the first power signal line through a first via hole, a second electrode of the first light emitting control transistor is electrically connected to a first electrode of the driving transistor, a first electrode of the second light emitting control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the second light emitting control transistor is electrically connected to the first connection portion through a second via; a first straight line extending along the first direction passes through at least one first via hole and at least one second via.
 3. The display substrate according to claim 2, wherein the pixel circuit further comprises a second connection portion, the second connection portion is arranged in the same layer as the second power signal line, the second connection portion is electrically connected to the first connection portion through a third via hole, and the second power signal line is electrically connected to the first power signal line through a fourth via; a second straight line extending along the first direction passes through at least one fourth via hole and at least one third via.
 4. The display substrate according to claim 3, wherein the plurality of sub-pixels comprise a plurality of first color sub-pixels, a plurality of second color sub-pixels and a plurality of third color sub-pixels, and in a direction perpendicular to the base substrate, the second electrode of the organic light emitting element of at least one of the plurality of third color sub-pixels overlaps with at least two data lines.
 5. The display substrate according to claim 4, wherein the second electrode of the organic light emitting element of the at least part of the plurality of sub-pixels comprises a main electrode and a connection electrode, the connection electrode is electrically connected to the second light emitting control transistor, the connection electrode of at least one of the plurality of second color sub-pixels and the connection electrode of at least one of the plurality of first color sub-pixels extend along the second direction, and the connection electrode of at least one of the plurality of third color sub-pixels extends along the first direction.
 6. The display substrate according to claim 1, wherein the first reset power signal line extends along the first direction, and the second reset power signal line extends along the second direction.
 7. The display substrate according to claim 1, wherein the first reset power signal line is disposed in the second conductive layer, and the second reset power signal line is disposed in the source-drain metal layer.
 8. The display substrate according to claim 5, wherein the connection electrode of the at least part of the plurality of sub-pixels is electrically connected to the second connection portion through a fifth via hole, the first conductive layer further comprises a light emitting control signal line extending along the first direction, the light emitting control signal line is electrically connected to gate electrodes of the first light emitting control transistor and the second light emitting control transistor, an orthographic projection of at least part of the second via hole of at least one sub-pixel on the base substrate is located at one side of an orthographic projection of the light emitting control signal line on the base substrate, and an orthographic projection of at least part of the fifth via hole on the base substrate is located at the other side of the orthographic projection of the light emitting control signal line on the base substrate.
 9. The display substrate according to claim 8, wherein, in at least one second color sub-pixel, the fifth via hole is closer to a center of the main electrode than the third via hole is; and in at least one first color sub-pixel, the fifth via hole is closer to a center of the main electrode than the third via hole is.
 10. The display substrate according to claim 4, wherein an orthographic projection of the second electrode of the organic light emitting element of the first color sub-pixel on a straight line extending along the first direction overlaps with orthographic projections of three first connection portions respectively located in three sub-pixels, and the three sub-pixels comprise one first color sub-pixel, one second color sub-pixel and one third color sub-pixel.
 11. The display substrate according to claim 4, wherein an orthographic projection of the second electrode of the organic light emitting element of the first color sub-pixel on a straight line extending along the first direction overlaps with orthographic projections of three second connection portions respectively located in three sub-pixels, and the three sub-pixels comprise one first color sub-pixel, one second color sub-pixel and one third color sub-pixel.
 12. The display substrate according to claim 4, wherein, in at least one of the plurality of third color sub-pixels, the second electrode of the organic light emitting element does not overlap with a channel of the driving transistor which controls the organic light emitting element of the third color sub-pixel in the direction perpendicular to the base substrate.
 13. The display substrate according to claim 4, wherein, in at least one of the plurality of first color sub-pixels, the second electrode of the organic light emitting element overlaps with a channel of the driving transistor which controls the organic light emitting element of the first color sub-pixel in the direction perpendicular to the base substrate.
 14. The display substrate according to claim 4, wherein, in at least one sub-pixel, the second electrode of the organic light emitting element exposes the third via.
 15. The display substrate according to claim 14, wherein, in each of the plurality of first color sub-pixels, an orthographic projection of the second electrode of the organic light emitting element on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate; in each of the plurality of second color sub-pixels, an orthographic projection of the second electrode of the organic light emitting element on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate; and in each of the plurality of third color sub-pixels, an orthographic projection of the second electrode of the organic light emitting element on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate.
 16. The display substrate according to claim 4, wherein among at least one of the plurality of first color sub-pixels, at least one of the plurality of second color sub-pixels and at least one of the plurality of third color sub-pixels, the pixel circuit further comprises a storage capacitor, a first electrode of the storage capacitor is located in the second conductive layer, a second electrode of the storage capacitor is located in the first conductive layer, and the first electrode of the storage capacitor and the second electrode of the storage capacitor overlap in the direction perpendicular to the base substrate and have an overlapping area; the overlapping area in the first color sub-pixel is the greatest among the at least one of the plurality of first color sub-pixels, the at least one of the plurality of second color sub-pixels and the at least one of the plurality of third color sub-pixels.
 17. The display substrate according to claim 1, wherein at least one first reset power signal line is electrically connected to at least one second reset power signal line, the first reset power signal line is electrically connected to the second reset power signal line through a sixth via.
 18. The display substrate according to claim 16, wherein the second conductive layer further comprises a signal pattern, the signal pattern is located between the first reset power signal line and the first electrode of the storage capacitor in the second direction, and the signal pattern is configured to access the reset signal.
 19. The display substrate according to claim 18, wherein the first conductive layer further comprises a scanning signal line extending along the first direction, the pixel circuit of the at least part of the plurality of sub-pixels further comprises a data writing transistor, a first electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, a second electrode of the data writing transistor is configured to be electrically connected to the data line to receive a data signal, and a gate electrode of the data writing transistor is configured to be electrically connected to the scanning signal line to receive a scan signal; the first reset power signal line extends along the first direction, and in the second direction, an orthographic projection of the signal pattern on the base substrate is located between an orthographic projection of the scanning signal line on the base substrate and an orthographic projection of the first reset power signal line on the base substrate.
 20. A display device, comprising the display substrate according to claim
 1. 